Linus Torvalds d91a46d680 RISC-V updates for v6.19-rc7 ... - Fix the RISC-V timer compare register update sequence on RV32 systems to use the recommended sequence in the RISC-V ISA manual. This avoids spurious interrupts during updates. - Add a dependence on the new CONFIG_CACHEMAINT_FOR_DMA Kconfig symbol for Renesas and StarFive RISC-V SoCs - Add a temporary workaround for a Clang compiler bug caused by using asm_goto_output for get_user() - Clarify our documentation to specifically state a particular ISA specification version for a chapter number reference -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEElRDoIDdEz9/svf2Kx4+xDQu9KksFAml1U4IACgkQx4+xDQu9 KkuGrg//VxWHcESotmJYSLBHAnR9jmwq/cubv/yX0WQuGqpAYVW8703F2QspvbxW iUa2SDMqiLodWvtz9T91exlNjcbbayyiltdmFeu+cj2vr1r5GRCrHDIFMwAhM6Yu zc0ZO/1Trmom75yNTC8A93X0AE9yYx71VWll7KvdPhng5Tewq1sKIYCZ33GKP7LN EkDWymE4tATK+Wz7Orb5Rm7krfJirf8jWkUYu7Br+rQ6WelHK/tc///wqGRluHit 7x8ca+86ASAVf9QZ73ODckc7h+rtXS5jGu3bBpXmr/BthpYc1awW/jrIFl7MbeXI ZHzNndijENnkl0ULsYOvGQOxy+PKtEfP70OQyRvmOqavMMaKLC/rkoBOosXPEpe/ Br9wMIFwUYWAyi8z2Wx0GV+rBTVQx+A83Y/ODq0b5kgXzOhRbQlc1WIQnhOGvXIr PDbxKQxdz/fQ19eJsR8Sr2JtDlORUxc8UjhkDY6BL30TYCYyhAhZUF9d2A6wZgGy dqrlG0mODwcKBJINZ+r0gyEW8DFkL7t99Ju1YiUK4eIO4Bequb7Q26KoUGriXwOy 7UPQ5d4svdxNnSwDkT73oUJop9Y34f0cNQmThKNaPTN2hulFzAVCdsLI0rCWAEzQ Z+XFncMkfAe3vnH9m/Vr/i5ndAHnMk5H09f5lZRn6KhtVedx0AM= =XHMU -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.19-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V fixes from Paul Walmsley: "The notable changes here are the three RISC-V timer compare register update sequence patches. These only apply to RV32 systems and are related to the 64-bit timer compare value being split across two separate 32-bit registers. We weren't using the appropriate three-write sequence, documented in the RISC-V ISA specifications, to avoid spurious timer interrupts during the update sequence; so, these patches now use the recommended sequence. This doesn't affect 64-bit RISC-V systems, since the timer compare value fits inside a single register and can be updated with a single write. - Fix the RISC-V timer compare register update sequence on RV32 systems to use the recommended sequence in the RISC-V ISA manual This avoids spurious interrupts during updates - Add a dependence on the new CONFIG_CACHEMAINT_FOR_DMA Kconfig symbol for Renesas and StarFive RISC-V SoCs - Add a temporary workaround for a Clang compiler bug caused by using asm_goto_output for get_user() - Clarify our documentation to specifically state a particular ISA specification version for a chapter number reference" * tag 'riscv-for-linus-6.19-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: Add intermediate cast to 'unsigned long' in __get_user_asm riscv: Use 64-bit variable for output in __get_user_asm soc: renesas: Fix missing dependency on new CONFIG_CACHEMAINT_FOR_DMA riscv: ERRATA_STARFIVE_JH7100: Fix missing dependency on new CONFIG_CACHEMAINT_FOR_DMA riscv: suspend: Fix stimecmp update hazard on RV32 riscv: kvm: Fix vstimecmp update hazard on RV32 riscv: clocksource: Fix stimecmp update hazard on RV32 Documentation: riscv: uabi: Clarify ISA spec version for canonical order		2026-01-24 18:55:48 -08:00
..
boot	riscv: boot: Always make Image from vmlinux, not vmlinux.unstripped	2025-12-30 19:57:55 -07:00
configs	riscv: configs: Clean up references to non-existing configs	2026-01-07 12:49:06 -07:00
crypto	lib/crypto: riscv: Depend on RISCV_EFFICIENT_VECTOR_UNALIGNED_ACCESS	2025-12-09 15:10:21 -08:00
errata	riscv: errata: Fix the PAUSE Opcode for MIPS P8700	2025-09-19 10:33:56 -06:00
include	riscv: Add intermediate cast to 'unsigned long' in __get_user_asm	2026-01-22 20:21:14 -07:00
kernel	riscv: suspend: Fix stimecmp update hazard on RV32	2026-01-14 17:43:22 -07:00
kvm	riscv: kvm: Fix vstimecmp update hazard on RV32	2026-01-14 17:43:07 -07:00
lib	riscv: checksum: Use riscv_has_extension_likely	2025-11-19 09:19:27 -07:00
mm	riscv: pgtable: Use riscv_has_extension_unlikely	2025-11-19 09:19:27 -07:00
net	riscv, bpf: Fix incorrect usage of BPF_TRAMP_F_ORIG_STACK	2026-01-06 11:40:48 -08:00
purgatory	kcfi: Rename CONFIG_CFI_CLANG to CONFIG_CFI	2025-09-24 14:29:14 -07:00
tools	riscv: Stop considering R_RISCV_NONE as bad relocations	2025-07-16 08:13:55 -07:00
Kbuild	riscv: migrate to the generic rule for built-in DTB	2025-03-18 13:30:13 +00:00
Kconfig	First set of RISC-V updates for v6.19-rc1	2025-12-05 16:26:57 -08:00
Kconfig.debug	riscv: Add tests for riscv module loading	2023-11-07 14:59:32 -08:00
Kconfig.errata	riscv: ERRATA_STARFIVE_JH7100: Fix missing dependency on new CONFIG_CACHEMAINT_FOR_DMA	2026-01-15 18:13:04 -07:00
Kconfig.socs	Initial Anlogic Platform Support	2025-11-21 21:29:57 +01:00
Kconfig.vendor	riscv: Add xmipsexectl as a vendor extension	2025-09-18 20:36:00 -06:00
Makefile	riscv: Remove redundant judgment for the default build target	2025-11-07 17:39:07 -07:00
Makefile.postlink	kbuild: Create intermediate vmlinux build with relocations preserved	2025-03-17 00:29:50 +09:00