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d2adcbdae5
As per the RZ/G3L Hardware manual, CPG_CLKON_ETH register bits{12,13} are
to control the RMII{tx, rx} clocks. Document the rmii{tx.rx} clocks for
RZ/G3L SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20260203104541.264759-1-biju.das.jz@bp.renesas.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
362 lines
9.1 KiB
YAML
362 lines
9.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/renesas,rzv2h-gbeth.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: GBETH glue layer for Renesas RZ/V2H(P) (and similar SoCs)
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maintainers:
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- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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select:
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properties:
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compatible:
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contains:
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enum:
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- renesas,r9a09g047-gbeth
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- renesas,r9a09g056-gbeth
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- renesas,r9a09g057-gbeth
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- renesas,r9a09g077-gbeth
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- renesas,r9a09g087-gbeth
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- renesas,rzv2h-gbeth
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required:
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- compatible
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properties:
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compatible:
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oneOf:
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- items:
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- const: renesas,r9a08g046-gbeth # RZ/G3L
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- const: snps,dwmac-5.30a
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- items:
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- enum:
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- renesas,r9a09g047-gbeth # RZ/G3E
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- renesas,r9a09g056-gbeth # RZ/V2N
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- renesas,r9a09g057-gbeth # RZ/V2H(P)
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- const: renesas,rzv2h-gbeth
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- const: snps,dwmac-5.20
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- items:
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- const: renesas,r9a09g077-gbeth # RZ/T2H
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- const: snps,dwmac-5.20
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- items:
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- const: renesas,r9a09g087-gbeth # RZ/N2H
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- const: renesas,r9a09g077-gbeth
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- const: snps,dwmac-5.20
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reg:
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maxItems: 1
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clocks:
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oneOf:
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- items:
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- description: CSR/Register access clock
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- description: AXI system/Main clock
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- description: PTP clock
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- description: TX clock
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- description: RX clock
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- description: TX clock phase-shifted by 180 degrees
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- description: RX clock phase-shifted by 180 degrees
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- description: RMII clock
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- description: RMII TX clock
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- description: RMII RX clock
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minItems: 7
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- items:
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- description: CSR clock
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- description: AXI system clock
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- description: TX clock
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clock-names:
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oneOf:
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- items:
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- const: stmmaceth
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- const: pclk
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- const: ptp_ref
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- const: tx
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- const: rx
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- const: tx-180
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- const: rx-180
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- const: rmii
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- const: rmii_tx
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- const: rmii_rx
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minItems: 7
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- items:
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- const: stmmaceth
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- const: pclk
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- const: tx
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interrupt-names:
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oneOf:
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- items:
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- const: macirq
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- const: eth_wake_irq
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- const: eth_lpi
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- const: rx-queue-0
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- const: rx-queue-1
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- const: rx-queue-2
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- const: rx-queue-3
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- const: tx-queue-0
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- const: tx-queue-1
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- const: tx-queue-2
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- const: tx-queue-3
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- items:
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- const: macirq
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- const: eth_wake_irq
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- const: eth_lpi
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- const: rx-queue-0
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- const: rx-queue-1
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- const: rx-queue-2
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- const: rx-queue-3
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- const: tx-queue-0
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- const: tx-queue-1
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- const: tx-queue-2
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- const: tx-queue-3
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- const: ptp-pps-0
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- const: ptp-pps-1
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- const: ptp-pps-2
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- const: ptp-pps-3
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- items:
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- const: macirq
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- const: eth_wake_irq
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- const: eth_lpi
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- const: rx-queue-0
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- const: rx-queue-1
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- const: rx-queue-2
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- const: rx-queue-3
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- const: rx-queue-4
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- const: rx-queue-5
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- const: rx-queue-6
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- const: rx-queue-7
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- const: tx-queue-0
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- const: tx-queue-1
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- const: tx-queue-2
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- const: tx-queue-3
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- const: tx-queue-4
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- const: tx-queue-5
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- const: tx-queue-6
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- const: tx-queue-7
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resets:
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oneOf:
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- items:
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- description: AXI power-on system reset
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- items:
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- description: AXI power-on system reset
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- description: AHB reset
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pcs-handle:
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description:
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phandle pointing to a PCS sub-node compatible with
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Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml#
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(Refer RZ/T2H portion in the DT-binding file)
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- resets
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allOf:
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- $ref: snps,dwmac.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r9a08g046-gbeth
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then:
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properties:
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clocks:
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minItems: 10
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clock-names:
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minItems: 10
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interrupts:
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minItems: 15
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maxItems: 15
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interrupt-names:
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minItems: 15
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maxItems: 15
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r9a09g077-gbeth
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then:
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properties:
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clocks:
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maxItems: 3
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clock-names:
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maxItems: 3
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interrupts:
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minItems: 19
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interrupt-names:
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minItems: 19
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resets:
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minItems: 2
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reset-names:
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minItems: 2
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required:
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- reset-names
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else:
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properties:
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resets:
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maxItems: 1
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pcs-handle: false
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reset-names: false
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- if:
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properties:
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compatible:
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contains:
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const: renesas,rzv2h-gbeth
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then:
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properties:
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clocks:
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maxItems: 7
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clock-names:
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maxItems: 7
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interrupts:
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minItems: 11
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maxItems: 11
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interrupt-names:
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minItems: 11
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maxItems: 11
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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ethernet@15c30000 {
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compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", "snps,dwmac-5.20";
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reg = <0x15c30000 0x10000>;
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clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>,
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<&ptp_clock>, <&cpg CPG_MOD 0xb8>,
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<&cpg CPG_MOD 0xb9>, <&cpg CPG_MOD 0xba>,
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<&cpg CPG_MOD 0xbb>;
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clock-names = "stmmaceth", "pclk", "ptp_ref",
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"tx", "rx", "tx-180", "rx-180";
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resets = <&cpg 0xb0>;
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interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
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"rx-queue-0", "rx-queue-1", "rx-queue-2",
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"rx-queue-3", "tx-queue-0", "tx-queue-1",
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"tx-queue-2", "tx-queue-3";
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phy-mode = "rgmii-id";
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snps,multicast-filter-bins = <256>;
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snps,perfect-filter-entries = <128>;
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rx-fifo-depth = <8192>;
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tx-fifo-depth = <8192>;
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snps,fixed-burst;
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snps,force_thresh_dma_mode;
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snps,axi-config = <&stmmac_axi_setup>;
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snps,mtl-rx-config = <&mtl_rx_setup>;
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snps,mtl-tx-config = <&mtl_tx_setup>;
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snps,txpbl = <32>;
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snps,rxpbl = <32>;
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phy-handle = <&phy0>;
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stmmac_axi_setup: stmmac-axi-config {
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snps,lpi_en;
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snps,wr_osr_lmt = <0xf>;
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snps,rd_osr_lmt = <0xf>;
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snps,blen = <16 8 4 0 0 0 0>;
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};
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mtl_rx_setup: rx-queues-config {
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snps,rx-queues-to-use = <4>;
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snps,rx-sched-sp;
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queue0 {
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snps,dcb-algorithm;
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snps,priority = <0x1>;
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snps,map-to-dma-channel = <0>;
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};
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queue1 {
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snps,dcb-algorithm;
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snps,priority = <0x2>;
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snps,map-to-dma-channel = <1>;
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};
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queue2 {
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snps,dcb-algorithm;
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snps,priority = <0x4>;
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snps,map-to-dma-channel = <2>;
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};
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queue3 {
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snps,dcb-algorithm;
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snps,priority = <0x8>;
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snps,map-to-dma-channel = <3>;
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};
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};
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mtl_tx_setup: tx-queues-config {
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snps,tx-queues-to-use = <4>;
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queue0 {
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snps,dcb-algorithm;
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snps,priority = <0x1>;
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};
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queue1 {
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snps,dcb-algorithm;
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snps,priority = <0x2>;
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};
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queue2 {
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snps,dcb-algorithm;
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snps,priority = <0x4>;
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};
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queue3 {
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snps,dcb-algorithm;
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snps,priority = <0x1>;
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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};
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