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Stafford Horne e318f5721d openrisc: dts: Add de0 nano multicore config and devicetree 
Add a multicore configuration for the Terasic de0 nano FPGA development
board.  This SoC runs 2 OpenRISC CPUs at 50Mhz with 32MB ram, UART for
console and GPIOs for LEDs.

This FPGA SoC is based on the simple-smp reference board and brings in
devices from the de0 nano common DTSI file.

A default config is added that brings together the device tree and
driver setup.

Link: https://github.com/stffrdhrn/de0_nano-multicore

Signed-off-by: Stafford Horne <shorne@gmail.com>
2026-01-16 16:38:56 +00:00
..
dts openrisc: dts: Add de0 nano multicore config and devicetree 2026-01-16 16:38:56 +00:00
.gitignore openrisc: Add vmlinux.bin target 2021-01-01 14:59:57 +09:00
Makefile openrisc: Add vmlinux.bin target 2021-01-01 14:59:57 +09:00