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Merge branch 'pci/controller/dwc-sophgo'

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- Disable L0s and L1 on Sophgo 2044 PCIe Root Ports (Inochi Amaoto)

* pci/controller/dwc-sophgo:
  PCI: sophgo: Disable L0s and L1 on Sophgo 2044 PCIe Root Ports
This commit is contained in:
Bjorn Helgaas 2026-02-06 17:09:48 -06:00
commit 5457880be1
1 changed files with 18 additions and 0 deletions
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18
drivers/pci/controller/dwc/pcie-sophgo.c
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@ -161,6 +161,22 @@ static void sophgo_pcie_msi_enable(struct dw_pcie_rp *pp)
raw_spin_unlock_irqrestore(&pp->lock, flags);
}
static void sophgo_pcie_disable_l0s_l1(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
u32 offset, val;
offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
dw_pcie_dbi_ro_wr_en(pci);
val = dw_pcie_readl_dbi(pci, PCI_EXP_LNKCAP + offset);
val &= ~(PCI_EXP_LNKCAP_ASPM_L0S | PCI_EXP_LNKCAP_ASPM_L1);
dw_pcie_writel_dbi(pci, PCI_EXP_LNKCAP + offset, val);
dw_pcie_dbi_ro_wr_dis(pci);
}
static int sophgo_pcie_host_init(struct dw_pcie_rp *pp)
{
int irq;
@ -171,6 +187,8 @@ static int sophgo_pcie_host_init(struct dw_pcie_rp *pp)
irq_set_chained_handler_and_data(irq, sophgo_pcie_intx_handler, pp);
sophgo_pcie_disable_l0s_l1(pp);
sophgo_pcie_msi_enable(pp);
return 0;