archives/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-03-08 03:24:45 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge branch 'pci/controller/dwc-rockchip'

Browse source 
- Disable unused BAR 0 and BAR 1 for Root Port (Shawn Lin)

* pci/controller/dwc-rockchip:
  PCI: dw-rockchip: Disable BAR 0 and BAR 1 for Root Port
This commit is contained in:
Bjorn Helgaas 2026-02-06 17:09:47 -06:00
commit 42e8a4ef13
1 changed files with 8 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

8
drivers/pci/controller/dwc/pcie-dw-rockchip.c
View file

@ -85,6 +85,8 @@
#define PCIE_LINKUP_MASK GENMASK(17, 16)
#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0)
#define PCIE_TYPE0_HDR_DBI2_OFFSET 0x100000
struct rockchip_pcie {
struct dw_pcie pci;
void __iomem *apb_base;
@ -312,6 +314,8 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)
if (irq < 0)
return irq;
pci->dbi_base2 = pci->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET;
ret = rockchip_pcie_init_irq_domain(rockchip);
if (ret < 0)
dev_err(dev, "failed to init irq domain\n");
@ -322,6 +326,10 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)
rockchip_pcie_configure_l1ss(pci);
rockchip_pcie_enable_l0s(pci);
/* Disable Root Ports BAR0 and BAR1 as they report bogus size */
dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, 0x0);
dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_1, 0x0);
return 0;
}