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Pin control changes for the v7.0 kernel cycle:

Browse source 
Core changes:
 
 - Drop the unused devm_pinctrl_unregister() function.
 
 - Move pretended generic pin control functionality out of the
   core and into the Amlogic AM4 driver. We have something better
   coming (hopefully).
 
 New hardware support:
 
 - Spacemit K3 (RISC-V) pin control support.
 
 - Atmel AT91 PIO4 (ARM32) SAMA7D65 pin control support.
 
 - Exynos9610 (ARM64) pin control support.
 
 - Qualcomm Mahua TLMM (ARM64) pin control support.
 
 - Microchip Polarfire MSSIO (RISC-V) pin control support.
 
 - Ocelot LAN9645XF (multiplatform) pin control support.
 
 Improvements:
 
 - Using a few more guards for locking.
 
 - Various nonurgent fixes and tweaks.
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Merge tag 'pinctrl-v7.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "Core changes:

   - Drop the unused devm_pinctrl_unregister() function

   - Move pretended generic pin control functionality out of the core
     and into the Amlogic AM4 driver. We have something better coming
     (hopefully)

  New hardware support:

   - Spacemit K3 (RISC-V) pin control support

   - Atmel AT91 PIO4 (ARM32) SAMA7D65 pin control support

   - Exynos9610 (ARM64) pin control support

   - Qualcomm Mahua TLMM (ARM64) pin control support

   - Microchip Polarfire MSSIO (RISC-V) pin control support

   - Ocelot LAN9645XF (multiplatform) pin control support

  Improvements:

   - Using a few more guards for locking

   - Various nonurgent fixes and tweaks"

* tag 'pinctrl-v7.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (73 commits)
  pinctrl: generic: move function to amlogic-am4 driver
  pinctrl: intel: Align Copyright note with corporate guidelines
  pinctrl: mediatek: remove unused drv_offset field
  pinctrl: canaan: k230: Fix NULL pointer dereference when parsing devicetree
  pinctrl: single: fix refcount leak in pcs_add_gpio_func()
  pinctrl: meson: amlogic-a4: Fix device node reference leak in bank helpers
  pinctrl: qcom: sm8250-lpass-lpi: Fix i2s2_data_groups definition
  pinctrl: core: Remove duplicate error messages
  pinctrl: core: Simplify devm_pinctrl_*()
  pinctrl: core: Remove unused devm_pinctrl_unregister()
  dt-bindings: pinctrl: spacemit: fix drive-strength check warning
  pinctrl: fix kismet issues with GENERIC_PINCTRL
  pinctrl: tangier: Join tng_pinctrl_probe() into its wrapper
  pinctrl: tangier: Remove duplicate error messages
  pinctrl: lynxpoint: Remove duplicate error messages
  pinctrl: cherryview: Remove duplicate error messages
  pinctrl: baytrail: Remove duplicate error messages
  pinctrl: intel: Remove duplicate error messages
  pinctrl: equilibrium: Fix device node reference leak in pinbank_init()
  dt-bindings: pinctrl: pinctrl-microchip-sgpio: add LAN969x
  ...
This commit is contained in:
Linus Torvalds 2026-02-16 09:35:24 -08:00
commit 46a1daac56
93 changed files with 2671 additions and 497 deletions
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2
Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
View file

@ -106,7 +106,7 @@ patternProperties:
# the pin numbers then,
# - Finally, the name will end with either -pin or pins.
"^([rs]-)?(([a-z0-9]{3,}|[a-oq-z][a-z0-9]*?)?-)+?(p[a-ilm][0-9]*?-)??pins?$":
"^([rs]-)?(([a-z0-9]{3,}|[a-oq-z0-9][a-z0-9]*?)?-)+?(p[a-ilm][0-9]*?-)??pins?$":
type: object
properties:

2
Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml
View file

@ -33,7 +33,7 @@ properties:
interrupts:
description:
Specifies the interrupt lines to be used by the controller.
Each interrupt line is shared by upto 4 GPIO lines.
Each interrupt line is shared by up to 4 GPIO lines.
maxItems: 8
interrupt-controller: true

109
Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-mssio.yaml Normal file
View file

@ -0,0 +1,109 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/microchip,mpfs-pinctrl-mssio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip Polarfire SoC MSSIO pinctrl
maintainers:
- Conor Dooley <conor.dooley@microchip.com>
properties:
compatible:
oneOf:
- const: microchip,mpfs-pinctrl-mssio
- items:
- const: microchip,pic64gx-pinctrl-mssio
- const: microchip,mpfs-pinctrl-mssio
reg:
maxItems: 1
pinctrl-use-default: true
patternProperties:
'-cfg$':
type: object
additionalProperties: false
patternProperties:
'-pins$':
type: object
additionalProperties: false
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
properties:
pins:
description:
The list of IOs that properties in the pincfg node apply to.
function:
description:
A string containing the name of the function to mux for these
pins. The "reserved" function tristates a pin.
enum: [ sd, emmc, qspi, spi, usb, uart, i2c, can, mdio, misc
reserved, gpio, fabric-test, tied-low, tied-high, tristate ]
bias-bus-hold: true
bias-disable: true
bias-pull-down: true
bias-pull-up: true
input-schmitt-enable: true
low-power-enable: true
drive-strength:
enum: [ 2, 4, 6, 8, 10, 12, 16, 20 ]
power-source:
description:
Which bank voltage to use. This cannot differ for pins in a
given bank, the whole bank uses the same voltage.
enum: [ 1200000, 1500000, 1800000, 2500000, 3300000 ]
microchip,clamp-diode:
$ref: /schemas/types.yaml#/definitions/flag
description:
Reflects the "Clamp Diode" setting in the MSS Configurator for
this pin. This setting controls whether or not input voltage
clamping should be enabled.
microchip,ibufmd:
$ref: /schemas/types.yaml#/definitions/uint32
default: 0
description:
Reflects the "IBUFMD" bits in the MSS Configurator output files
for this pin.
required:
- pins
- function
- power-source
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pinctrl@204 {
compatible = "microchip,mpfs-pinctrl-mssio";
reg = <0x204 0x7c>;
ikrd-spi1-cfg {
spi1-pins {
pins = <30>, <31>, <32>, <33>;
function = "spi";
bias-pull-up;
drive-strength = <8>;
power-source = <3300000>;
microchip,ibufmd = <0x1>;
};
};
};
...

20
Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
View file

@ -21,10 +21,15 @@ properties:
pattern: '^gpio@[0-9a-f]+$'
compatible:
enum:
- microchip,sparx5-sgpio
- mscc,ocelot-sgpio
- mscc,luton-sgpio
oneOf:
- enum:
- microchip,sparx5-sgpio
- mscc,ocelot-sgpio
- mscc,luton-sgpio
- items:
- enum:
- microchip,lan9691-sgpio
- const: microchip,sparx5-sgpio
'#address-cells':
const: 1
@ -80,7 +85,12 @@ patternProperties:
type: object
properties:
compatible:
const: microchip,sparx5-sgpio-bank
oneOf:
- items:
- enum:
- microchip,lan9691-sgpio-bank
- const: microchip,sparx5-sgpio-bank
- const: microchip,sparx5-sgpio-bank
reg:
description: |

6
Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
View file

@ -14,6 +14,7 @@ properties:
compatible:
oneOf:
- enum:
- microchip,lan96455f-pinctrl
- microchip,lan966x-pinctrl
- microchip,lan9691-pinctrl
- microchip,sparx5-pinctrl
@ -30,6 +31,11 @@ properties:
- microchip,lan9693-pinctrl
- microchip,lan9692-pinctrl
- const: microchip,lan9691-pinctrl
- items:
- enum:
- microchip,lan96457f-pinctrl
- microchip,lan96459f-pinctrl
- const: microchip,lan96455f-pinctrl
reg:
items:

6
Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml
View file

@ -10,14 +10,16 @@ maintainers:
- Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
description:
Top Level Mode Multiplexer pin controller in Qualcomm Glymur SoC.
Top Level Mode Multiplexer pin controller in Qualcomm Glymur and Mahua SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,glymur-tlmm
enum:
- qcom,glymur-tlmm
- qcom,mahua-tlmm
reg:
maxItems: 1

13
Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
View file

@ -49,6 +49,17 @@ properties:
gpio-ranges:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
description:
The first cell contains the global GPIO port index, constructed using the
RZT2H_GPIO() helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
and the second cell is used to specify the flag.
E.g. "interrupts = <RZT2H_GPIO(8, 6) IRQ_TYPE_EDGE_FALLING>;" if P08_6 is
being used as an interrupt.
clocks:
maxItems: 1
@ -139,6 +150,8 @@ examples:
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 288>;
interrupt-controller;
#interrupt-cells = <2>;
power-domains = <&cpg>;
serial0-pins {

1
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
View file

@ -48,6 +48,7 @@ properties:
- enum:
- google,gs101-wakeup-eint
- samsung,exynos2200-wakeup-eint
- samsung,exynos9610-wakeup-eint
- samsung,exynos9810-wakeup-eint
- samsung,exynos990-wakeup-eint
- samsung,exynosautov9-wakeup-eint

1
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
View file

@ -55,6 +55,7 @@ properties:
- samsung,exynos850-pinctrl
- samsung,exynos8890-pinctrl
- samsung,exynos8895-pinctrl
- samsung,exynos9610-pinctrl
- samsung,exynos9810-pinctrl
- samsung,exynos990-pinctrl
- samsung,exynosautov9-pinctrl

27
Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml
View file

@ -11,7 +11,9 @@ maintainers:
properties:
compatible:
const: spacemit,k1-pinctrl
enum:
- spacemit,k1-pinctrl
- spacemit,k3-pinctrl
reg:
items:
@ -30,6 +32,10 @@ properties:
resets:
maxItems: 1
spacemit,apbc:
$ref: /schemas/types.yaml#/definitions/phandle
description: Phandle to syscon that access the protected register
patternProperties:
'-cfg$':
type: object
@ -72,10 +78,20 @@ patternProperties:
enum: [ 0, 1 ]
drive-strength:
description: |
typical current when output high level.
1.8V output: 11, 21, 32, 42 (mA)
3.3V output: 7, 10, 13, 16, 19, 23, 26, 29 (mA)
description:
typical current (in mA) when the output at high level.
anyOf:
- enum: [ 11, 21, 32, 42 ]
description: For K1 SoC, 1.8V voltage output
- enum: [ 7, 10, 13, 16, 19, 23, 26, 29 ]
description: For K1 SoC, 3.3V voltage output
- enum: [ 2, 4, 6, 7, 9, 11, 13, 14, 21, 23, 25, 26, 28, 30, 31, 33 ]
description: For K3 SoC, 1.8V voltage output
- enum: [ 3, 5, 7, 9, 11, 13, 15, 17, 25, 27, 29, 31, 33, 35, 37, 38 ]
description: For K3 SoC, 3.3V voltage output
input-schmitt:
description: |
@ -126,6 +142,7 @@ examples:
clocks = <&syscon_apbc 42>,
<&syscon_apbc 94>;
clock-names = "func", "bus";
spacemit,apbc = <&syscon_apbc>;
uart0_2_cfg: uart0-2-cfg {
uart0-2-pins {

4
Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml
View file

@ -42,6 +42,10 @@ properties:
type: object
$ref: /schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml
pinctrl@204:
type: object
$ref: /schemas/pinctrl/microchip,mpfs-pinctrl-mssio.yaml
required:
- compatible
- reg

1
Documentation/driver-api/driver-model/devres.rst
View file

@ -408,7 +408,6 @@ PINCTRL
devm_pinctrl_get_select()
devm_pinctrl_register()
devm_pinctrl_register_and_init()
devm_pinctrl_unregister()
POWER
devm_reboot_mode_register()