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cleanups and fixes

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Merge tag 'mips_7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Thomas Bogendoerfer:
 "Cleanups and fixes"

* tag 'mips_7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (28 commits)
  Revert "clk: microchip: core: allow driver to be compiled with COMPILE_TEST"
  Revert "clk: microchip: fix typo in reference to a config option"
  MIPS: Implement ARCH_HAS_CC_CAN_LINK
  MIPS: rb532: Fix MMIO UART resource registration
  MIPS: Work around LLVM bug when gp is used as global register variable
  MIPS: Loongson64: env: Fixup serial clock-frequency when using LEFI
  MIPS: Loongson2ef: Use pcibios_align_resource() to block io range
  MIPS: Loongson2ef: Register PCI controller in early stage
  clk: microchip: fix typo in reference to a config option
  MIPS: Loongson64: dts: fix phy-related definition of LS7A GMAC
  clk: microchip: core: allow driver to be compiled with COMPILE_TEST
  MIPS: drop unused pic32.h header
  watchdog: pic32-wdt: update include to use pic32.h from platform_data
  watchdog: pic32-dmt: update include to use pic32.h from platform_data
  serial: pic32_uart: update include to use pic32.h from platform_data
  rtc: pic32: update include to use pic32.h from platform_data
  pinctrl: pic32: update include to use pic32.h from platform_data
  mmc: sdhci-pic32: update include to use pic32.h from platform_data
  irqchip/irq-pic32-evic: update include to use pic32.h from platform_data
  clk: microchip: core: update include to use pic32.h from platform_data
  ...
This commit is contained in:
Linus Torvalds 2026-02-16 09:30:44 -08:00
commit 6086f349a3
23 changed files with 191 additions and 38 deletions
Download patch file Download diff file Expand all files Collapse all files

1
MAINTAINERS
View file

@ -17611,6 +17611,7 @@ F: Documentation/arch/mips/
F: arch/mips/
F: drivers/platform/mips/
F: include/dt-bindings/mips/
F: include/linux/platform_data/pic32.h
MIPS BOSTON DEVELOPMENT BOARD
M: Paul Burton <paulburton@kernel.org>

29
arch/mips/Kconfig
View file

@ -4,6 +4,7 @@ config MIPS
default y
select ARCH_32BIT_OFF_T if !64BIT
select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
select ARCH_HAS_CC_CAN_LINK
select ARCH_HAS_CPU_CACHE_ALIASING
select ARCH_HAS_CPU_FINALIZE_INIT
select ARCH_HAS_CURRENT_STACK_POINTER
@ -1409,7 +1410,6 @@ config CPU_LOONGSON32
select CPU_MIPS32
select CPU_MIPSR2
select CPU_HAS_PREFETCH
select CPU_HAS_LOAD_STORE_LR
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_CPUFREQ
@ -3127,6 +3127,33 @@ config CC_HAS_MNO_BRANCH_LIKELY
config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
def_bool y if CC_IS_CLANG
config ARCH_CC_CAN_LINK_N32
bool
default $(cc_can_link_user,-mabi=n32 -EL) if MIPS32_N32 && CPU_LITTLE_ENDIAN
default $(cc_can_link_user,-mabi=n32 -EB) if MIPS32_N32 && CPU_BIG_ENDIAN
config ARCH_CC_CAN_LINK_N64
bool
default $(cc_can_link_user,-mabi=64 -EL) if 64BIT && CPU_LITTLE_ENDIAN
default $(cc_can_link_user,-mabi=64 -EB) if 64BIT && CPU_BIG_ENDIAN
config ARCH_CC_CAN_LINK_O32
bool
default $(cc_can_link_user,-mabi=32 -EL) if (32BIT || MIPS32_O32) && CPU_LITTLE_ENDIAN
default $(cc_can_link_user,-mabi=32 -EB) if (32BIT || MIPS32_O32) && CPU_BIG_ENDIAN
config ARCH_CC_CAN_LINK
def_bool ARCH_CC_CAN_LINK_N32 || ARCH_CC_CAN_LINK_N64 || ARCH_CC_CAN_LINK_O32
config ARCH_USERFLAGS
string
default "-mabi=n32 -EL" if ARCH_CC_CAN_LINK_N32 && CPU_LITTLE_ENDIAN
default "-mabi=n32 -EB" if ARCH_CC_CAN_LINK_N32 && CPU_BIG_ENDIAN
default "-mabi=64 -EL" if ARCH_CC_CAN_LINK_N64 && CPU_LITTLE_ENDIAN
default "-mabi=64 -EB" if ARCH_CC_CAN_LINK_N64 && CPU_BIG_ENDIAN
default "-mabi=32 -EL" if ARCH_CC_CAN_LINK_O32 && CPU_LITTLE_ENDIAN
default "-mabi=32 -EB" if ARCH_CC_CAN_LINK_O32 && CPU_BIG_ENDIAN
menu "Power management options"
config ARCH_HIBERNATION_POSSIBLE

6
arch/mips/boot/dts/loongson/ls7a-pch.dtsi
View file

@ -199,7 +199,8 @@
<13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_lpi";
interrupt-parent = <&pic>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
@ -222,7 +223,8 @@
<15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_lpi";
interrupt-parent = <&pic>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
phy-handle = <&phy1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;

6
arch/mips/include/asm/mach-loongson2ef/loongson.h
View file

@ -324,4 +324,10 @@ extern unsigned long _loongson_addrwincfg_base;
#endif /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
#ifdef CONFIG_PCI
void loongson2ef_pcibios_init(void);
#else
static inline void loongson2ef_pcibios_init(void) { }
#endif
#endif /* __ASM_MACH_LOONGSON2EF_LOONGSON_H */

2
arch/mips/include/asm/mach-loongson64/topology.h
View file

@ -7,7 +7,7 @@
#define cpu_to_node(cpu) (cpu_logical_map(cpu) >> 2)
extern cpumask_t __node_cpumask[];
#define cpumask_of_node(node) (&__node_cpumask[node])
#define cpumask_of_node(node) ((node) == NUMA_NO_NODE ? cpu_all_mask : &__node_cpumask[node])
struct pci_bus;
extern int pcibus_to_node(struct pci_bus *);

13
arch/mips/kernel/relocate.c
View file

@ -420,7 +420,20 @@ void *__init relocate_kernel(void)
goto out;
/* The current thread is now within the relocated image */
#ifndef CONFIG_CC_IS_CLANG
__current_thread_info = RELOCATED(&init_thread_union);
#else
/*
* LLVM may wrongly restore $gp ($28) in epilog even if it's
* intentionally modified. Work around this by using inline
* assembly to assign $gp. $gp couldn't be listed as output or
* clobber, or LLVM will still restore its original value.
* See also LLVM upstream issue
* https://github.com/llvm/llvm-project/issues/176546
*/
asm volatile("move $28, %0" : :
"r" (RELOCATED(&init_thread_union)));
#endif
/* Return the new kernel's entry point */
kernel_entry = RELOCATED(start_kernel);

18
arch/mips/loongson2ef/common/pci.c
View file

@ -17,7 +17,7 @@ static struct resource loongson_pci_mem_resource = {
static struct resource loongson_pci_io_resource = {
.name = "pci io space",
.start = LOONGSON_PCI_IO_START,
.start = 0x00000000UL, /* See loongson2ef_pcibios_init(). */
.end = IO_SPACE_LIMIT,
.flags = IORESOURCE_IO,
};
@ -73,15 +73,19 @@ static void __init setup_pcimap(void)
#endif
}
static int __init pcibios_init(void)
void __init loongson2ef_pcibios_init(void)
{
setup_pcimap();
/*
* ISA-mode only IDE controllers have a hard dependency on ISA IO ports.
*
* Claim them by setting PCI IO space to start at 0x00000000, and set
* PCIBIOS_MIN_IO to prevent non-legacy PCI devices from touching
* reserved regions.
*/
PCIBIOS_MIN_IO = LOONGSON_PCI_IO_START;
loongson_pci_controller.io_map_base = mips_io_port_base;
register_pci_controller(&loongson_pci_controller);
return 0;
}
arch_initcall(pcibios_init);

1
arch/mips/loongson2ef/common/setup.c
View file

@ -27,4 +27,5 @@ EXPORT_SYMBOL(__wbflush);
void __init plat_mem_setup(void)
{
loongson2ef_pcibios_init();
}

98
arch/mips/loongson64/env.c
View file

@ -16,6 +16,7 @@
#include <linux/dma-map-ops.h>
#include <linux/export.h>
#include <linux/libfdt.h>
#include <linux/pci_ids.h>
#include <linux/string_choices.h>
#include <asm/bootinfo.h>
@ -57,6 +58,101 @@ void __init prom_dtb_init_env(void)
loongson_fdt_blob = (void *)fw_arg2;
}
static int __init lefi_fixup_fdt_serial(void *fdt, u64 uart_addr, u32 uart_clk)
{
int node, len, depth = -1;
const fdt64_t *reg;
fdt32_t *clk;
for (node = fdt_next_node(fdt, -1, &depth);
node >= 0 && depth >= 0;
node = fdt_next_node(fdt, node, &depth)) {
reg = fdt_getprop(fdt, node, "reg", &len);
if (!reg || len <= 8 || fdt64_ld(reg) != uart_addr)
continue;
clk = fdt_getprop_w(fdt, node, "clock-frequency", &len);
if (!clk) {
pr_warn("UART 0x%llx misses clock-frequency property\n",
uart_addr);
return -ENOENT;
} else if (len != 4) {
pr_warn("UART 0x%llx has invalid clock-frequency property\n",
uart_addr);
return -EINVAL;
}
fdt32_st(clk, uart_clk);
return 0;
}
return -ENODEV;
}
static void __init lefi_fixup_fdt(struct system_loongson *system)
{
static unsigned char fdt_buf[16 << 10] __initdata;
struct uart_device *uartdev;
bool is_loongson64g;
u64 uart_base;
int ret, i;
ret = fdt_open_into(loongson_fdt_blob, fdt_buf, sizeof(fdt_buf));
if (ret) {
pr_err("Failed to open FDT to fix up\n");
return;
}
is_loongson64g = (read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G;
for (i = 0; i < system->nr_uarts; i++) {
uartdev = &system->uarts[i];
ret = lefi_fixup_fdt_serial(fdt_buf, uartdev->uart_base,
uartdev->uartclk);
/*
* LOONGSON64G's CPU serials are mapped to two different
* addresses, one full-featured but differs from
* previous generations, one fully compatible with them.
*
* It's unspecified that which mapping should uart_base refer
* to, thus we should try fixing up with both.
*/
if (ret == -ENODEV && is_loongson64g) {
switch (uartdev->uart_base) {
case 0x1fe00100:
uart_base = 0x1fe001e0;
break;
case 0x1fe00110:
uart_base = 0x1fe001e8;
break;
case 0x1fe001e0:
uart_base = 0x1fe00100;
break;
case 0x1fe001e8:
uart_base = 0x1fe00110;
break;
default:
pr_err("Unexpected UART address 0x%llx passed by firmware\n",
uartdev->uart_base);
ret = -EINVAL;
goto err_fixup;
}
ret = lefi_fixup_fdt_serial(fdt_buf, uart_base,
uartdev->uartclk);
}
err_fixup:
if (ret)
pr_err("Couldn't fix up FDT node for UART 0x%llx\n",
uartdev->uart_base);
}
loongson_fdt_blob = fdt_buf;
}
void __init prom_lefi_init_env(void)
{
struct boot_params *boot_p;
@ -237,4 +333,6 @@ void __init prom_lefi_init_env(void)
if (!loongson_fdt_blob)
pr_err("Failed to determine built-in Loongson64 dtb\n");
else
lefi_fixup_fdt(esys);
}

3
arch/mips/pic32/common/reset.c
View file

@ -4,9 +4,10 @@
* Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_data/pic32.h>
#include <linux/pm.h>
#include <asm/reboot.h>
#include <asm/mach-pic32/pic32.h>
#define PIC32_RSWRST 0x10

3
arch/mips/pic32/pic32mzda/config.c
View file

@ -5,10 +5,9 @@
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_data/pic32.h>
#include <linux/spinlock.h>
#include <asm/mach-pic32/pic32.h>
#include "pic32mzda.h"
#define PIC32_CFGCON 0x0000

3
arch/mips/pic32/pic32mzda/early_clk.c
View file

@ -3,7 +3,8 @@
* Joshua Henderson <joshua.henderson@microchip.com>
* Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
*/
#include <asm/mach-pic32/pic32.h>
#include <linux/io.h>
#include <linux/platform_data/pic32.h>
#include "pic32mzda.h"

3
arch/mips/pic32/pic32mzda/early_console.c
View file

@ -3,7 +3,8 @@
* Joshua Henderson <joshua.henderson@microchip.com>
* Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
*/
#include <asm/mach-pic32/pic32.h>
#include <linux/io.h>
#include <linux/platform_data/pic32.h>
#include <asm/fw/fw.h>
#include <asm/setup.h>

5
arch/mips/rb532/devices.c
View file

@ -213,11 +213,12 @@ static struct platform_device rb532_wdt = {
static struct plat_serial8250_port rb532_uart_res[] = {
{
.type = PORT_16550A,
.membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
.mapbase = REGBASE + UART0BASE,
.mapsize = 0x1000,
.irq = UART0_IRQ,
.regshift = 2,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
},
{
.flags = 0,

2
drivers/clk/microchip/clk-core.c
View file

@ -9,7 +9,7 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <asm/mach-pic32/pic32.h>
#include <linux/platform_data/pic32.h>
#include "clk-core.h"

2
drivers/irqchip/irq-pic32-evic.c
View file

@ -13,10 +13,10 @@
#include <linux/io.h>
#include <linux/irqchip.h>
#include <linux/irq.h>
#include <linux/platform_data/pic32.h>
#include <asm/irq.h>
#include <asm/traps.h>
#include <asm/mach-pic32/pic32.h>
#define REG_INTCON 0x0000
#define REG_INTSTAT 0x0020

2
drivers/mmc/host/sdhci-pic32.c
View file

@ -18,6 +18,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/platform_data/sdhci-pic32.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/slab.h>
@ -25,7 +26,6 @@
#include <linux/io.h>
#include "sdhci.h"
#include "sdhci-pltfm.h"
#include <linux/platform_data/sdhci-pic32.h>
#define SDH_SHARED_BUS_CTRL 0x000000E0
#define SDH_SHARED_BUS_NR_CLK_PINS_MASK 0x7

3
drivers/pinctrl/pinctrl-pic32.c
View file

@ -15,13 +15,12 @@
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_data/pic32.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <asm/mach-pic32/pic32.h>
#include "pinctrl-utils.h"
#include "pinctrl-pic32.h"

3
drivers/rtc/rtc-pic32.c
View file

@ -15,8 +15,7 @@
#include <linux/clk.h>
#include <linux/rtc.h>
#include <linux/bcd.h>
#include <asm/mach-pic32/pic32.h>
#include <linux/platform_data/pic32.h>
#define PIC32_RTCCON 0x00
#define PIC32_RTCCON_ON BIT(15)

3
drivers/tty/serial/pic32_uart.c
View file

@ -22,8 +22,7 @@
#include <linux/tty_flip.h>
#include <linux/serial_core.h>
#include <linux/delay.h>
#include <asm/mach-pic32/pic32.h>
#include <linux/platform_data/pic32.h>
/* UART name and device definitions */
#define PIC32_DEV_NAME "pic32-uart"

3
drivers/watchdog/pic32-dmt.c
View file

@ -12,12 +12,11 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_data/pic32.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/watchdog.h>
#include <asm/mach-pic32/pic32.h>
/* Deadman Timer Regs */
#define DMTCON_REG 0x00
#define DMTPRECLR_REG 0x10

3
drivers/watchdog/pic32-wdt.c
View file

@ -12,12 +12,11 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_data/pic32.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/watchdog.h>
#include <asm/mach-pic32/pic32.h>
/* Watchdog Timer Registers */
#define WDTCON_REG 0x00

17
arch/mips/include/asm/mach-pic32/pic32.h → include/linux/platform_data/pic32.h
View file

@ -3,10 +3,10 @@
* Joshua Henderson <joshua.henderson@microchip.com>
* Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
*/
#ifndef _ASM_MACH_PIC32_H
#define _ASM_MACH_PIC32_H
#ifndef __LINUX_PLATFORM_DATA_PIC32_H
#define __LINUX_PLATFORM_DATA_PIC32_H
#include <linux/io.h>
#include <linux/types.h>
/*
* PIC32 register offsets for SET/CLR/INV where supported.
@ -26,11 +26,14 @@
#define PIC32_BASE_PORT 0x1f860000
#define PIC32_BASE_DEVCFG2 0x1fc4ff44
/*
* Register unlock sequence required for some register access.
*/
#if defined(CONFIG_MACH_PIC32)
/* Register unlock sequence required for some register access. */
void pic32_syskey_unlock_debug(const char *fn, const ulong ln);
#define pic32_syskey_unlock() \
pic32_syskey_unlock_debug(__func__, __LINE__)
#else
/* COMPILE_TEST on all other architectures */
#define pic32_syskey_unlock()
#endif
#endif /* _ASM_MACH_PIC32_H */
#endif /* __LINUX_PLATFORM_DATA_PIC32_H */