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The MTK VCP mailbox enables the SoC to communicate with the VCP by passing messages through 64 32-bit wide registers. It has 32 interrupt vectors in either direction for signalling purposes. This adds a binding for Mediatek VCP mailbox. Signed-off-by: Jjian Zhou <jjian.zhou@mediatek.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
49 lines
1.1 KiB
YAML
49 lines
1.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mailbox/mediatek,mt8196-vcp-mbox.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Video Companion Processor (VCP) mailbox
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maintainers:
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- Jjian Zhou <Jjian.Zhou@mediatek.com>
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description:
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The MTK VCP mailbox enables the SoC to communicate with the VCP by passing
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messages through 64 32-bit wide registers. It has 32 interrupt vectors in
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either direction for signalling purposes.
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properties:
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compatible:
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enum:
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- mediatek,mt8196-vcp-mbox
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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"#mbox-cells":
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const: 0
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required:
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- compatible
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- reg
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- interrupts
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- "#mbox-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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mailbox@31b80000 {
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compatible = "mediatek,mt8196-vcp-mbox";
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reg = <0x31b80000 0x1000>;
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interrupts = <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH 0>;
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#mbox-cells = <0>;
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};
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