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e5b250214a
The PORTSC1 register has a different offset in Tegra20 compared to Tegra30+, yet they share a crucial set of registers required for HSIC functionality. Reflect this register offset change in the SoC config. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Link: https://patch.msgid.link/20260202080526.23487-5-clamor95@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
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| asm-generic | ||
| clocksource | ||
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| cxl | ||
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| hyperv | ||
| keys | ||
| kunit | ||
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| linux | ||
| math-emu | ||
| media | ||
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| misc | ||
| net | ||
| pcmcia | ||
| ras | ||
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