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bf4afc53b7
This was done entirely with mindless brute force, using
git grep -l '\<k[vmz]*alloc_objs*(.*, GFP_KERNEL)' |
xargs sed -i 's/\(alloc_objs*(.*\), GFP_KERNEL)/\1)/'
to convert the new alloc_obj() users that had a simple GFP_KERNEL
argument to just drop that argument.
Note that due to the extreme simplicity of the scripting, any slightly
more complex cases spread over multiple lines would not be triggered:
they definitely exist, but this covers the vast bulk of the cases, and
the resulting diff is also then easier to check automatically.
For the same reason the 'flex' versions will be done as a separate
conversion.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
256 lines
5.9 KiB
C
256 lines
5.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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*
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* Parts of this file are based on Ralink's 2.6.21 BSP
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*
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2013 John Crispin <john@phrozen.org>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/bug.h>
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#include <linux/slab.h>
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#include <linux/sys_soc.h>
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#include <asm/mipsregs.h>
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#include <asm/mach-ralink/ralink_regs.h>
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#include <asm/mach-ralink/mt7620.h>
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#include "common.h"
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/* analog */
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#define PMU0_CFG 0x88
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#define PMU_SW_SET BIT(28)
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#define A_DCDC_EN BIT(24)
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#define A_SSC_PERI BIT(19)
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#define A_SSC_GEN BIT(18)
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#define A_SSC_M 0x3
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#define A_SSC_S 16
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#define A_DLY_M 0x7
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#define A_DLY_S 8
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#define A_VTUNE_M 0xff
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/* digital */
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#define PMU1_CFG 0x8C
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#define DIG_SW_SEL BIT(25)
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/* EFUSE bits */
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#define EFUSE_MT7688 0x100000
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/* DRAM type bit */
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#define DRAM_TYPE_MT7628_MASK 0x1
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/* does the board have sdram or ddram */
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static int dram_type;
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static struct ralink_soc_info *soc_info_ptr;
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static __init void
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mt7620_dram_init(struct ralink_soc_info *soc_info)
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{
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switch (dram_type) {
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case SYSCFG0_DRAM_TYPE_SDRAM:
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pr_info("Board has SDRAM\n");
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soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
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soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
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break;
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case SYSCFG0_DRAM_TYPE_DDR1:
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pr_info("Board has DDR1\n");
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soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
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soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
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break;
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case SYSCFG0_DRAM_TYPE_DDR2:
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pr_info("Board has DDR2\n");
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soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
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soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
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break;
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default:
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BUG();
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}
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}
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static __init void
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mt7628_dram_init(struct ralink_soc_info *soc_info)
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{
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switch (dram_type) {
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case SYSCFG0_DRAM_TYPE_DDR1_MT7628:
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pr_info("Board has DDR1\n");
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soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
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soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
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break;
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case SYSCFG0_DRAM_TYPE_DDR2_MT7628:
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pr_info("Board has DDR2\n");
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soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
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soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
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break;
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default:
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BUG();
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}
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}
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static unsigned int __init mt7620_get_soc_name0(void)
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{
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return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME0);
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}
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static unsigned int __init mt7620_get_soc_name1(void)
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{
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return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME1);
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}
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static bool __init mt7620_soc_valid(void)
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{
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if (mt7620_get_soc_name0() == MT7620_CHIP_NAME0 &&
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mt7620_get_soc_name1() == MT7620_CHIP_NAME1)
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return true;
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else
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return false;
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}
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static bool __init mt7628_soc_valid(void)
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{
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if (mt7620_get_soc_name0() == MT7620_CHIP_NAME0 &&
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mt7620_get_soc_name1() == MT7628_CHIP_NAME1)
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return true;
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else
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return false;
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}
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static unsigned int __init mt7620_get_rev(void)
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{
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return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_REV);
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}
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static unsigned int __init mt7620_get_bga(void)
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{
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return (mt7620_get_rev() >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
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}
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static unsigned int __init mt7620_get_efuse(void)
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{
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return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_EFUSE_CFG);
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}
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static unsigned int __init mt7620_get_soc_ver(void)
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{
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return (mt7620_get_rev() >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK;
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}
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static unsigned int __init mt7620_get_soc_eco(void)
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{
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return (mt7620_get_rev() & CHIP_REV_ECO_MASK);
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}
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static const char __init *mt7620_get_soc_name(struct ralink_soc_info *soc_info)
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{
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if (mt7620_soc_valid()) {
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u32 bga = mt7620_get_bga();
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if (bga) {
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ralink_soc = MT762X_SOC_MT7620A;
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soc_info->compatible = "ralink,mt7620a-soc";
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return "MT7620A";
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} else {
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ralink_soc = MT762X_SOC_MT7620N;
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soc_info->compatible = "ralink,mt7620n-soc";
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return "MT7620N";
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}
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} else if (mt7628_soc_valid()) {
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u32 efuse = mt7620_get_efuse();
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unsigned char *name = NULL;
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if (efuse & EFUSE_MT7688) {
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ralink_soc = MT762X_SOC_MT7688;
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name = "MT7688";
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} else {
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ralink_soc = MT762X_SOC_MT7628AN;
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name = "MT7628AN";
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}
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soc_info->compatible = "ralink,mt7628an-soc";
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return name;
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} else {
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panic("mt762x: unknown SoC, n0:%08x n1:%08x\n",
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mt7620_get_soc_name0(), mt7620_get_soc_name1());
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}
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}
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static const char __init *mt7620_get_soc_id_name(void)
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{
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if (ralink_soc == MT762X_SOC_MT7620A)
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return "mt7620a";
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else if (ralink_soc == MT762X_SOC_MT7620N)
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return "mt7620n";
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else if (ralink_soc == MT762X_SOC_MT7688)
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return "mt7688";
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else if (ralink_soc == MT762X_SOC_MT7628AN)
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return "mt7628n";
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else
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return "invalid";
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}
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static int __init mt7620_soc_dev_init(void)
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{
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struct soc_device *soc_dev;
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struct soc_device_attribute *soc_dev_attr;
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soc_dev_attr = kzalloc_obj(*soc_dev_attr);
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if (!soc_dev_attr)
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return -ENOMEM;
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soc_dev_attr->family = "Ralink";
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soc_dev_attr->soc_id = mt7620_get_soc_id_name();
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soc_dev_attr->data = soc_info_ptr;
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soc_dev = soc_device_register(soc_dev_attr);
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if (IS_ERR(soc_dev)) {
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kfree(soc_dev_attr);
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return PTR_ERR(soc_dev);
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}
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return 0;
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}
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device_initcall(mt7620_soc_dev_init);
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void __init prom_soc_init(struct ralink_soc_info *soc_info)
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{
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const char *name = mt7620_get_soc_name(soc_info);
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u32 cfg0;
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u32 pmu0;
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u32 pmu1;
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snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
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"MediaTek %s ver:%u eco:%u",
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name, mt7620_get_soc_ver(), mt7620_get_soc_eco());
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cfg0 = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_SYSTEM_CONFIG0);
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if (is_mt76x8()) {
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dram_type = cfg0 & DRAM_TYPE_MT7628_MASK;
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} else {
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dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) &
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SYSCFG0_DRAM_TYPE_MASK;
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if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN)
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dram_type = SYSCFG0_DRAM_TYPE_SDRAM;
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}
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soc_info->mem_base = MT7620_DRAM_BASE;
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if (is_mt76x8())
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mt7628_dram_init(soc_info);
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else
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mt7620_dram_init(soc_info);
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pmu0 = __raw_readl(MT7620_SYSC_BASE + PMU0_CFG);
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pmu1 = __raw_readl(MT7620_SYSC_BASE + PMU1_CFG);
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pr_info("Analog PMU set to %s control\n",
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(pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
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pr_info("Digital PMU set to %s control\n",
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(pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
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soc_info_ptr = soc_info;
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}
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