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bf4afc53b7
This was done entirely with mindless brute force, using
git grep -l '\<k[vmz]*alloc_objs*(.*, GFP_KERNEL)' |
xargs sed -i 's/\(alloc_objs*(.*\), GFP_KERNEL)/\1)/'
to convert the new alloc_obj() users that had a simple GFP_KERNEL
argument to just drop that argument.
Note that due to the extreme simplicity of the scripting, any slightly
more complex cases spread over multiple lines would not be triggered:
they definitely exist, but this covers the vast bulk of the cases, and
the resulting diff is also then easier to check automatically.
For the same reason the 'flex' versions will be done as a separate
conversion.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
264 lines
7.8 KiB
C
264 lines
7.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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*
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* Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
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* Copyright (C) 2011 John Crispin <john@phrozen.org>
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*/
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#include <linux/ioport.h>
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#include <linux/export.h>
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#include <linux/clkdev.h>
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#include <linux/of_address.h>
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#include <asm/delay.h>
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#include <lantiq_soc.h>
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#include "../clk.h"
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#include "../prom.h"
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/* infrastructure control register */
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#define SYS1_INFRAC 0x00bc
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/* Configuration fuses for drivers and pll */
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#define STATUS_CONFIG 0x0040
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/* GPE frequency selection */
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#define GPPC_OFFSET 24
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#define GPEFREQ_MASK 0x0000C00
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#define GPEFREQ_OFFSET 10
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/* Clock status register */
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#define SYSCTL_CLKS 0x0000
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/* Clock enable register */
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#define SYSCTL_CLKEN 0x0004
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/* Clock clear register */
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#define SYSCTL_CLKCLR 0x0008
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/* Activation Status Register */
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#define SYSCTL_ACTS 0x0020
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/* Activation Register */
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#define SYSCTL_ACT 0x0024
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/* Deactivation Register */
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#define SYSCTL_DEACT 0x0028
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/* reboot Register */
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#define SYSCTL_RBT 0x002c
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/* CPU0 Clock Control Register */
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#define SYS1_CPU0CC 0x0040
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/* HRST_OUT_N Control Register */
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#define SYS1_HRSTOUTC 0x00c0
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/* clock divider bit */
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#define CPU0CC_CPUDIV 0x0001
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/* Activation Status Register */
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#define ACTS_ASC0_ACT 0x00001000
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#define ACTS_SSC0 0x00002000
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#define ACTS_ASC1_ACT 0x00000800
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#define ACTS_I2C_ACT 0x00004000
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#define ACTS_P0 0x00010000
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#define ACTS_P1 0x00010000
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#define ACTS_P2 0x00020000
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#define ACTS_P3 0x00020000
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#define ACTS_P4 0x00040000
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#define ACTS_PADCTRL0 0x00100000
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#define ACTS_PADCTRL1 0x00100000
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#define ACTS_PADCTRL2 0x00200000
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#define ACTS_PADCTRL3 0x00200000
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#define ACTS_PADCTRL4 0x00400000
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#define sysctl_w32(m, x, y) ltq_w32((x), sysctl_membase[m] + (y))
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#define sysctl_r32(m, x) ltq_r32(sysctl_membase[m] + (x))
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#define sysctl_w32_mask(m, clear, set, reg) \
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sysctl_w32(m, (sysctl_r32(m, reg) & ~(clear)) | (set), reg)
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#define status_w32(x, y) ltq_w32((x), status_membase + (y))
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#define status_r32(x) ltq_r32(status_membase + (x))
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static void __iomem *sysctl_membase[3], *status_membase;
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void __iomem *ltq_sys1_membase, *ltq_ebu_membase;
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static inline void sysctl_wait(struct clk *clk,
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unsigned int test, unsigned int reg)
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{
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int err = 1000000;
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do {} while (--err && ((sysctl_r32(clk->module, reg)
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& clk->bits) != test));
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if (!err)
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pr_err("module de/activation failed %d %08X %08X %08X\n",
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clk->module, clk->bits, test,
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sysctl_r32(clk->module, reg) & clk->bits);
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}
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static int sysctl_activate(struct clk *clk)
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{
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sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN);
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sysctl_w32(clk->module, clk->bits, SYSCTL_ACT);
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sysctl_wait(clk, clk->bits, SYSCTL_ACTS);
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return 0;
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}
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static void sysctl_deactivate(struct clk *clk)
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{
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sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR);
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sysctl_w32(clk->module, clk->bits, SYSCTL_DEACT);
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sysctl_wait(clk, 0, SYSCTL_ACTS);
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}
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static int sysctl_clken(struct clk *clk)
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{
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sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN);
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sysctl_w32(clk->module, clk->bits, SYSCTL_ACT);
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sysctl_wait(clk, clk->bits, SYSCTL_CLKS);
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return 0;
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}
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static void sysctl_clkdis(struct clk *clk)
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{
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sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR);
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sysctl_wait(clk, 0, SYSCTL_CLKS);
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}
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static void sysctl_reboot(struct clk *clk)
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{
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unsigned int act;
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unsigned int bits;
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act = sysctl_r32(clk->module, SYSCTL_ACT);
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bits = ~act & clk->bits;
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if (bits != 0) {
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sysctl_w32(clk->module, bits, SYSCTL_CLKEN);
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sysctl_w32(clk->module, bits, SYSCTL_ACT);
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sysctl_wait(clk, bits, SYSCTL_ACTS);
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}
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sysctl_w32(clk->module, act & clk->bits, SYSCTL_RBT);
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sysctl_wait(clk, clk->bits, SYSCTL_ACTS);
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}
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/* enable the ONU core */
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static void falcon_gpe_enable(void)
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{
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unsigned int freq;
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unsigned int status;
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/* if the clock is already enabled */
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status = sysctl_r32(SYSCTL_SYS1, SYS1_INFRAC);
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if (status & (1 << (GPPC_OFFSET + 1)))
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return;
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freq = (status_r32(STATUS_CONFIG) &
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GPEFREQ_MASK) >>
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GPEFREQ_OFFSET;
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if (freq == 0)
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freq = 1; /* use 625MHz on unfused chip */
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/* apply new frequency */
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sysctl_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1),
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freq << (GPPC_OFFSET + 2) , SYS1_INFRAC);
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udelay(1);
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/* enable new frequency */
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sysctl_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC);
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udelay(1);
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}
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static inline void clkdev_add_sys(const char *dev, unsigned int module,
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unsigned int bits)
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{
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struct clk *clk = kzalloc_obj(struct clk);
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if (!clk)
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return;
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clk->cl.dev_id = dev;
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clk->cl.con_id = NULL;
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clk->cl.clk = clk;
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clk->module = module;
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clk->bits = bits;
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clk->activate = sysctl_activate;
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clk->deactivate = sysctl_deactivate;
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clk->enable = sysctl_clken;
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clk->disable = sysctl_clkdis;
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clk->reboot = sysctl_reboot;
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clkdev_add(&clk->cl);
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}
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void __init ltq_soc_init(void)
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{
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struct device_node *np_status =
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of_find_compatible_node(NULL, NULL, "lantiq,status-falcon");
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struct device_node *np_ebu =
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of_find_compatible_node(NULL, NULL, "lantiq,ebu-falcon");
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struct device_node *np_sys1 =
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of_find_compatible_node(NULL, NULL, "lantiq,sys1-falcon");
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struct device_node *np_syseth =
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of_find_compatible_node(NULL, NULL, "lantiq,syseth-falcon");
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struct device_node *np_sysgpe =
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of_find_compatible_node(NULL, NULL, "lantiq,sysgpe-falcon");
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struct resource res_status, res_ebu, res_sys[3];
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int i;
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/* check if all the core register ranges are available */
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if (!np_status || !np_ebu || !np_sys1 || !np_syseth || !np_sysgpe)
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panic("Failed to load core nodes from devicetree");
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if (of_address_to_resource(np_status, 0, &res_status) ||
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of_address_to_resource(np_ebu, 0, &res_ebu) ||
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of_address_to_resource(np_sys1, 0, &res_sys[0]) ||
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of_address_to_resource(np_syseth, 0, &res_sys[1]) ||
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of_address_to_resource(np_sysgpe, 0, &res_sys[2]))
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panic("Failed to get core resources");
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of_node_put(np_status);
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of_node_put(np_ebu);
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of_node_put(np_sys1);
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of_node_put(np_syseth);
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of_node_put(np_sysgpe);
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if ((!request_mem_region(res_status.start, resource_size(&res_status),
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res_status.name)) ||
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(!request_mem_region(res_ebu.start, resource_size(&res_ebu),
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res_ebu.name)) ||
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(!request_mem_region(res_sys[0].start, resource_size(&res_sys[0]),
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res_sys[0].name)) ||
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(!request_mem_region(res_sys[1].start, resource_size(&res_sys[1]),
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res_sys[1].name)) ||
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(!request_mem_region(res_sys[2].start, resource_size(&res_sys[2]),
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res_sys[2].name)))
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pr_err("Failed to request core resources");
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status_membase = ioremap(res_status.start,
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resource_size(&res_status));
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ltq_ebu_membase = ioremap(res_ebu.start,
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resource_size(&res_ebu));
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if (!status_membase || !ltq_ebu_membase)
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panic("Failed to remap core resources");
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for (i = 0; i < 3; i++) {
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sysctl_membase[i] = ioremap(res_sys[i].start,
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resource_size(&res_sys[i]));
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if (!sysctl_membase[i])
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panic("Failed to remap sysctrl resources");
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}
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ltq_sys1_membase = sysctl_membase[0];
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falcon_gpe_enable();
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/* get our 3 static rates for cpu, fpi and io clocks */
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if (ltq_sys1_r32(SYS1_CPU0CC) & CPU0CC_CPUDIV)
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clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M, 0);
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else
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clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M, 0);
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/* add our clock domains */
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clkdev_add_sys("1d810000.gpio", SYSCTL_SYSETH, ACTS_P0);
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clkdev_add_sys("1d810100.gpio", SYSCTL_SYSETH, ACTS_P2);
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clkdev_add_sys("1e800100.gpio", SYSCTL_SYS1, ACTS_P1);
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clkdev_add_sys("1e800200.gpio", SYSCTL_SYS1, ACTS_P3);
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clkdev_add_sys("1e800300.gpio", SYSCTL_SYS1, ACTS_P4);
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clkdev_add_sys("1db01000.pad", SYSCTL_SYSETH, ACTS_PADCTRL0);
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clkdev_add_sys("1db02000.pad", SYSCTL_SYSETH, ACTS_PADCTRL2);
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clkdev_add_sys("1e800400.pad", SYSCTL_SYS1, ACTS_PADCTRL1);
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clkdev_add_sys("1e800500.pad", SYSCTL_SYS1, ACTS_PADCTRL3);
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clkdev_add_sys("1e800600.pad", SYSCTL_SYS1, ACTS_PADCTRL4);
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clkdev_add_sys("1e100b00.serial", SYSCTL_SYS1, ACTS_ASC1_ACT);
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clkdev_add_sys("1e100c00.serial", SYSCTL_SYS1, ACTS_ASC0_ACT);
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clkdev_add_sys("1e100d00.spi", SYSCTL_SYS1, ACTS_SSC0);
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clkdev_add_sys("1e200000.i2c", SYSCTL_SYS1, ACTS_I2C_ACT);
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}
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