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bf4afc53b7
This was done entirely with mindless brute force, using
git grep -l '\<k[vmz]*alloc_objs*(.*, GFP_KERNEL)' |
xargs sed -i 's/\(alloc_objs*(.*\), GFP_KERNEL)/\1)/'
to convert the new alloc_obj() users that had a simple GFP_KERNEL
argument to just drop that argument.
Note that due to the extreme simplicity of the scripting, any slightly
more complex cases spread over multiple lines would not be triggered:
they definitely exist, but this covers the vast bulk of the cases, and
the resulting diff is also then easier to check automatically.
For the same reason the 'flex' versions will be done as a separate
conversion.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
145 lines
3.3 KiB
C
145 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* linux/arch/arm/mach-sa1100/clock.c
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <mach/hardware.h>
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#include <mach/generic.h>
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static const char * const clk_tucr_parents[] = {
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"clk32768", "clk3686400",
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};
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static DEFINE_SPINLOCK(tucr_lock);
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static int clk_gpio27_enable(struct clk_hw *hw)
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{
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unsigned long flags;
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/*
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* First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
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* (SA-1110 Developer's Manual, section 9.1.2.1)
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*/
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local_irq_save(flags);
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GAFR |= GPIO_32_768kHz;
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GPDR |= GPIO_32_768kHz;
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local_irq_restore(flags);
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return 0;
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}
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static void clk_gpio27_disable(struct clk_hw *hw)
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{
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unsigned long flags;
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local_irq_save(flags);
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GPDR &= ~GPIO_32_768kHz;
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GAFR &= ~GPIO_32_768kHz;
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local_irq_restore(flags);
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}
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static const struct clk_ops clk_gpio27_ops = {
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.enable = clk_gpio27_enable,
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.disable = clk_gpio27_disable,
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};
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static const char * const clk_gpio27_parents[] = {
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"tucr-mux",
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};
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static const struct clk_init_data clk_gpio27_init_data __initconst = {
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.name = "gpio27",
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.ops = &clk_gpio27_ops,
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.parent_names = clk_gpio27_parents,
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.num_parents = ARRAY_SIZE(clk_gpio27_parents),
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};
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/*
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* Derived from the table 8-1 in the SA1110 manual, the MPLL appears to
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* multiply its input rate by 4 x (4 + PPCR). This calculation gives
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* the exact rate. The figures given in the table are the rates rounded
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* to 100kHz. Stick with sa11x0_getspeed() for the time being.
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*/
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static unsigned long clk_mpll_recalc_rate(struct clk_hw *hw,
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unsigned long prate)
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{
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return sa11x0_getspeed(0) * 1000;
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}
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static const struct clk_ops clk_mpll_ops = {
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.recalc_rate = clk_mpll_recalc_rate,
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};
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static const char * const clk_mpll_parents[] = {
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"clk3686400",
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};
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static const struct clk_init_data clk_mpll_init_data __initconst = {
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.name = "mpll",
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.ops = &clk_mpll_ops,
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.parent_names = clk_mpll_parents,
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.num_parents = ARRAY_SIZE(clk_mpll_parents),
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.flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL,
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};
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int __init sa11xx_clk_init(void)
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{
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struct clk_hw *hw;
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int ret;
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hw = clk_hw_register_fixed_rate(NULL, "clk32768", NULL, 0, 32768);
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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clk_hw_register_clkdev(hw, NULL, "sa1100-rtc");
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hw = clk_hw_register_fixed_rate(NULL, "clk3686400", NULL, 0, 3686400);
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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clk_hw_register_clkdev(hw, "OSTIMER0", NULL);
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hw = kzalloc_obj(*hw);
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if (!hw)
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return -ENOMEM;
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hw->init = &clk_mpll_init_data;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(hw);
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return ret;
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}
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clk_hw_register_clkdev(hw, NULL, "sa11x0-fb");
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clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia");
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clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia.0");
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clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia.1");
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clk_hw_register_clkdev(hw, NULL, "1800");
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hw = clk_hw_register_mux(NULL, "tucr-mux", clk_tucr_parents,
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ARRAY_SIZE(clk_tucr_parents), 0,
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(void __iomem *)&TUCR, FShft(TUCR_TSEL),
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FAlnMsk(TUCR_TSEL), 0, &tucr_lock);
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clk_set_rate(hw->clk, 3686400);
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hw = kzalloc_obj(*hw);
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if (!hw)
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return -ENOMEM;
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hw->init = &clk_gpio27_init_data;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(hw);
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return ret;
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}
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clk_hw_register_clkdev(hw, NULL, "sa1111.0");
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return 0;
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}
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