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The QUICC Engine provides interrupts for a few I/O ports. This is handled via a separate interrupt ID and managed via a triplet of dedicated registers hosted by the SoC. Implement an interrupt driver for it so that those IRQs can then be linked to the related GPIOs. Link: https://lore.kernel.org/r/63f19db21a91729d91b3df336a56a7eb4206e561.1767804922.git.chleroy@kernel.org Signed-off-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
14 lines
456 B
Makefile
14 lines
456 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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#
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# Makefile for the linux ppc-specific parts of QE
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#
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obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o
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obj-$(CONFIG_CPM) += qe_common.o
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obj-$(CONFIG_CPM_TSA) += tsa.o
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obj-$(CONFIG_CPM_QMC) += qmc.o
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obj-$(CONFIG_UCC) += ucc.o
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obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
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obj-$(CONFIG_UCC_FAST) += ucc_fast.o
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obj-$(CONFIG_QE_TDM) += qe_tdm.o
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obj-$(CONFIG_QE_USB) += usb.o
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obj-$(CONFIG_QE_GPIO) += gpio.o qe_ports_ic.o
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