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LPDDR and DDR bindings are SDRAM types and are likely to share the same properties (at least for density, io-width and reg). To avoid bindings duplication, factorise the properties. The compatible description has been updated because the MR (Mode registers) used to get manufacturer ID and revision ID are not present in case of DDR. Those information should be in a SPD (Serial Presence Detect) EEPROM in case of DIMM module or are known in case of soldered memory chips as they are in the datasheet of the memory chips. Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com> Link: https://patch.msgid.link/20251118-b4-ddr-bindings-v9-1-a033ac5144da@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
204 lines
5.8 KiB
YAML
204 lines
5.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
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maintainers:
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- Krzysztof Kozlowski <krzk@kernel.org>
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allOf:
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- $ref: jedec,sdram-props.yaml#
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- elpida,ECB240ABACN
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- elpida,B8132B2PB-6D-F
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- enum:
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- jedec,lpddr2-nvm
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- jedec,lpddr2-s2
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- jedec,lpddr2-s4
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- items:
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- pattern: "^lpddr2-[0-9a-f]{2},[0-9a-f]{4}$"
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- enum:
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- jedec,lpddr2-nvm
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- jedec,lpddr2-s2
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- jedec,lpddr2-s4
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revision-id1:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 255
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description: |
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Revision 1 value of SDRAM chip. Obtained from device datasheet.
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Property is deprecated, use revision-id instead.
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deprecated: true
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revision-id2:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 255
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description: |
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Revision 2 value of SDRAM chip. Obtained from device datasheet.
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Property is deprecated, use revision-id instead.
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deprecated: true
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tRRD-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 16
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description: |
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Active bank a to active bank b in terms of number of clock cycles.
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Obtained from device datasheet.
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tWTR-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 16
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description: |
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Internal WRITE-to-READ command delay in terms of number of clock cycles.
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Obtained from device datasheet.
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tXP-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 16
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description: |
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Exit power-down to next valid command delay in terms of number of clock
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cycles. Obtained from device datasheet.
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tRTP-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 16
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description: |
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Internal READ to PRECHARGE command delay in terms of number of clock
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cycles. Obtained from device datasheet.
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tCKE-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 16
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description: |
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CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
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of clock cycles. Obtained from device datasheet.
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tRPab-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 16
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description: |
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Row precharge time (all banks) in terms of number of clock cycles.
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Obtained from device datasheet.
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tRCD-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 16
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description: |
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RAS-to-CAS delay in terms of number of clock cycles. Obtained from
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device datasheet.
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tWR-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 16
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description: |
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WRITE recovery time in terms of number of clock cycles. Obtained from
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device datasheet.
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tRASmin-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 16
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description: |
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Row active time in terms of number of clock cycles. Obtained from device
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datasheet.
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tCKESR-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 16
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description: |
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CKE minimum pulse width during SELF REFRESH (low pulse width during
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SELF REFRESH) in terms of number of clock cycles. Obtained from device
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datasheet.
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tFAW-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 16
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description: |
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Four-bank activate window in terms of number of clock cycles. Obtained
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from device datasheet.
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patternProperties:
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"^lpddr2-timings":
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$ref: jedec,lpddr2-timings.yaml
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description: |
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The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
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"lpddr2-timings" provides AC timing parameters of the device for
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a given speed-bin. The user may provide the timings for as many
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speed-bins as is required.
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required:
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- compatible
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- density
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- io-width
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unevaluatedProperties: false
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examples:
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- |
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elpida_ECB240ABACN: lpddr2 {
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compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4";
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density = <2048>;
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io-width = <32>;
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revision-id = <1 0>;
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tRPab-min-tck = <3>;
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tRCD-min-tck = <3>;
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tWR-min-tck = <3>;
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tRASmin-min-tck = <3>;
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tRRD-min-tck = <2>;
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tWTR-min-tck = <2>;
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tXP-min-tck = <2>;
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tRTP-min-tck = <2>;
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tCKE-min-tck = <3>;
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tCKESR-min-tck = <3>;
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tFAW-min-tck = <8>;
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timings_elpida_ECB240ABACN_400mhz: lpddr2-timings0 {
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compatible = "jedec,lpddr2-timings";
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min-freq = <10000000>;
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max-freq = <400000000>;
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tRPab = <21000>;
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tRCD = <18000>;
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tWR = <15000>;
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tRAS-min = <42000>;
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tRRD = <10000>;
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tWTR = <7500>;
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tXP = <7500>;
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tRTP = <7500>;
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tCKESR = <15000>;
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tDQSCK-max = <5500>;
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tFAW = <50000>;
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tZQCS = <90000>;
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tZQCL = <360000>;
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tZQinit = <1000000>;
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tRAS-max-ns = <70000>;
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};
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timings_elpida_ECB240ABACN_200mhz: lpddr2-timings1 {
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compatible = "jedec,lpddr2-timings";
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min-freq = <10000000>;
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max-freq = <200000000>;
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tRPab = <21000>;
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tRCD = <18000>;
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tWR = <15000>;
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tRAS-min = <42000>;
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tRRD = <10000>;
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tWTR = <10000>;
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tXP = <7500>;
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tRTP = <7500>;
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tCKESR = <15000>;
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tDQSCK-max = <5500>;
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tFAW = <50000>;
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tZQCS = <90000>;
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tZQCL = <360000>;
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tZQinit = <1000000>;
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tRAS-max-ns = <70000>;
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};
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};
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