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5b28991395
For SuperSpeed USB to work properly, there is a set of HW settings that need to be programmed into the USB blocks within the QMP PHY. Ensure that these settings follow the latest settings mentioned in the HW programming guide. The QMP USB PHY on Glymur is a USB43 based PHY that will have some new ways to define certain registers, such as the replacement of TXA/RXA and TXB/RXB register sets. This was replaced with the LALB register set. There are also some PHY init updates to modify the PCS MISC register space. Without these, the QMP PHY PLL locking fails. Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://patch.msgid.link/20251209-linux-next-12825-v8-8-42133596bda0@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
93 lines
2.3 KiB
C
93 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_H_
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#define QCOM_PHY_QMP_H_
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#include "phy-qcom-qmp-qserdes-com.h"
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#include "phy-qcom-qmp-qserdes-txrx.h"
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#include "phy-qcom-qmp-qserdes-com-v2.h"
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#include "phy-qcom-qmp-qserdes-txrx-v2.h"
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#include "phy-qcom-qmp-qserdes-com-v3.h"
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#include "phy-qcom-qmp-qserdes-txrx-v3.h"
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#include "phy-qcom-qmp-qserdes-com-v4.h"
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#include "phy-qcom-qmp-qserdes-txrx-v4.h"
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#include "phy-qcom-qmp-qserdes-txrx-v4_20.h"
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#include "phy-qcom-qmp-qserdes-com-v5.h"
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#include "phy-qcom-qmp-qserdes-txrx-v5.h"
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#include "phy-qcom-qmp-qserdes-txrx-v5_20.h"
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#include "phy-qcom-qmp-qserdes-txrx-v5_5nm.h"
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#include "phy-qcom-qmp-qserdes-com-v6.h"
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#include "phy-qcom-qmp-qserdes-txrx-v6.h"
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#include "phy-qcom-qmp-qserdes-txrx-v6_20.h"
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#include "phy-qcom-qmp-qserdes-txrx-v6_n4.h"
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#include "phy-qcom-qmp-qserdes-ln-shrd-v5.h"
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#include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
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#include "phy-qcom-qmp-qserdes-com-v7.h"
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#include "phy-qcom-qmp-qserdes-txrx-v7.h"
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#include "phy-qcom-qmp-qserdes-com-v8.h"
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#include "phy-qcom-qmp-usb43-qserdes-com-v8.h"
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#include "phy-qcom-qmp-qserdes-txrx-v8.h"
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#include "phy-qcom-qmp-qserdes-lalb-v8.h"
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#include "phy-qcom-qmp-qserdes-pll.h"
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#include "phy-qcom-qmp-pcs-v2.h"
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#include "phy-qcom-qmp-pcs-v3.h"
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#include "phy-qcom-qmp-pcs-v4.h"
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#include "phy-qcom-qmp-pcs-v4_20.h"
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#include "phy-qcom-qmp-pcs-v5.h"
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#include "phy-qcom-qmp-pcs-v5_20.h"
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#include "phy-qcom-qmp-pcs-v6.h"
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#include "phy-qcom-qmp-pcs-v6-n4.h"
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#include "phy-qcom-qmp-pcs-v6_20.h"
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#include "phy-qcom-qmp-pcs-v7.h"
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#include "phy-qcom-qmp-pcs-v8.h"
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#include "phy-qcom-qmp-pcs-v8_50.h"
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/* QPHY_SW_RESET bit */
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#define SW_RESET BIT(0)
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/* QPHY_POWER_DOWN_CONTROL */
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#define SW_PWRDN BIT(0)
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#define REFCLK_DRV_DSBL BIT(1) /* PCIe */
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/* QPHY_START_CONTROL bits */
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#define SERDES_START BIT(0)
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#define PCS_START BIT(1)
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/* QPHY_PCS_STATUS bit */
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#define PHYSTATUS BIT(6)
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#define PHYSTATUS_4_20 BIT(7)
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/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
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#define ARCVR_DTCT_EN BIT(0)
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#define ALFPS_DTCT_EN BIT(1)
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#define ARCVR_DTCT_EVENT_SEL BIT(4)
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/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
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#define IRQ_CLEAR BIT(0)
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/* QPHY_PCS_MISC_CLAMP_ENABLE register bits */
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#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
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#endif
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