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5b28991395
For SuperSpeed USB to work properly, there is a set of HW settings that need to be programmed into the USB blocks within the QMP PHY. Ensure that these settings follow the latest settings mentioned in the HW programming guide. The QMP USB PHY on Glymur is a USB43 based PHY that will have some new ways to define certain registers, such as the replacement of TXA/RXA and TXB/RXB register sets. This was replaced with the LALB register set. There are also some PHY init updates to modify the PCS MISC register space. Without these, the QMP PHY PLL locking fails. Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://patch.msgid.link/20251209-linux-next-12825-v8-8-42133596bda0@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
224 lines
12 KiB
C
224 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_USB43_QSERDES_COM_V8_H_
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#define QCOM_PHY_QMP_USB43_QSERDES_COM_V8_H_
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#define QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE1 0x000
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#define QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE1 0x004
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#define QSERDES_V8_USB43_COM_SSC_STEP_SIZE3_MODE1 0x008
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#define QSERDES_V8_USB43_COM_CLK_EP_DIV_MODE1 0x00c
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#define QSERDES_V8_USB43_COM_CP_CTRL_MODE1 0x010
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#define QSERDES_V8_USB43_COM_PLL_RCTRL_MODE1 0x014
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#define QSERDES_V8_USB43_COM_PLL_CCTRL_MODE1 0x018
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#define QSERDES_V8_USB43_COM_CORECLK_DIV_MODE1 0x01c
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#define QSERDES_V8_USB43_COM_LOCK_CMP1_MODE1 0x020
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#define QSERDES_V8_USB43_COM_LOCK_CMP2_MODE1 0x024
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#define QSERDES_V8_USB43_COM_DEC_START_MODE1 0x028
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#define QSERDES_V8_USB43_COM_DEC_START_MSB_MODE1 0x02c
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#define QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE1 0x030
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#define QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE1 0x034
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#define QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE1 0x038
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#define QSERDES_V8_USB43_COM_HSCLK_SEL_1 0x03c
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#define QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE1 0x040
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#define QSERDES_V8_USB43_COM_INTEGLOOP_GAIN1_MODE1 0x044
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#define QSERDES_V8_USB43_COM_VCO_TUNE1_MODE1 0x048
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#define QSERDES_V8_USB43_COM_VCO_TUNE2_MODE1 0x04c
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#define QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x050
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#define QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x054
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#define QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x058
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#define QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x05c
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#define QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0 0x060
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#define QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0 0x064
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#define QSERDES_V8_USB43_COM_SSC_STEP_SIZE3_MODE0 0x068
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#define QSERDES_V8_USB43_COM_CLK_EP_DIV_MODE0 0x06c
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#define QSERDES_V8_USB43_COM_CP_CTRL_MODE0 0x070
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#define QSERDES_V8_USB43_COM_PLL_RCTRL_MODE0 0x074
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#define QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0 0x078
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#define QSERDES_V8_USB43_COM_CORECLK_DIV_MODE0 0x07c
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#define QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0 0x080
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#define QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0 0x084
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#define QSERDES_V8_USB43_COM_DEC_START_MODE0 0x088
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#define QSERDES_V8_USB43_COM_DEC_START_MSB_MODE0 0x08c
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#define QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE0 0x090
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#define QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0 0x094
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#define QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0 0x098
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#define QSERDES_V8_USB43_COM_HSCLK_HS_SWITCH_SEL_1 0x09c
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#define QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE0 0x0a0
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#define QSERDES_V8_USB43_COM_INTEGLOOP_GAIN1_MODE0 0x0a4
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#define QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0 0x0a8
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#define QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0 0x0ac
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#define QSERDES_V8_USB43_COM_ATB_SEL1 0x0b0
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#define QSERDES_V8_USB43_COM_ATB_SEL2 0x0b4
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#define QSERDES_V8_USB43_COM_FREQ_UPDATE 0x0b8
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#define QSERDES_V8_USB43_COM_BG_TIMER 0x0bc
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#define QSERDES_V8_USB43_COM_SSC_EN_CENTER 0x0c0
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#define QSERDES_V8_USB43_COM_SSC_ADJ_PER1 0x0c4
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#define QSERDES_V8_USB43_COM_SSC_ADJ_PER2 0x0c8
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#define QSERDES_V8_USB43_COM_SSC_PER1 0x0cc
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#define QSERDES_V8_USB43_COM_SSC_PER2 0x0d0
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#define QSERDES_V8_USB43_COM_POST_DIV 0x0d4
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#define QSERDES_V8_USB43_COM_POST_DIV_MUX 0x0d8
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#define QSERDES_V8_USB43_COM_BIAS_EN_CLKBUFLR_EN 0x0dc
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#define QSERDES_V8_USB43_COM_CLK_ENABLE1 0x0e0
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#define QSERDES_V8_USB43_COM_SYS_CLK_CTRL 0x0e4
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#define QSERDES_V8_USB43_COM_SYSCLK_BUF_ENABLE 0x0e8
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#define QSERDES_V8_USB43_COM_PLL_EN 0x0ec
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#define QSERDES_V8_USB43_COM_DEBUG_BUS_OVRD 0x0f0
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#define QSERDES_V8_USB43_COM_PLL_IVCO 0x0f4
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#define QSERDES_V8_USB43_COM_PLL_IVCO_MODE1 0x0f8
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#define QSERDES_V8_USB43_COM_CMN_IETRIM 0x0fc
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#define QSERDES_V8_USB43_COM_CMN_IPTRIM 0x100
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#define QSERDES_V8_USB43_COM_EP_CLOCK_DETECT_CTRL 0x104
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#define QSERDES_V8_USB43_COM_PLL_CNTRL 0x108
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#define QSERDES_V8_USB43_COM_BIAS_EN_CTRL_BY_PSM 0x10c
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#define QSERDES_V8_USB43_COM_SYSCLK_EN_SEL 0x110
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#define QSERDES_V8_USB43_COM_CML_SYSCLK_SEL 0x114
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#define QSERDES_V8_USB43_COM_RESETSM_CNTRL 0x118
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#define QSERDES_V8_USB43_COM_RESETSM_CNTRL2 0x11c
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#define QSERDES_V8_USB43_COM_LOCK_CMP_EN 0x120
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#define QSERDES_V8_USB43_COM_LOCK_CMP_CFG 0x124
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#define QSERDES_V8_USB43_COM_INTEGLOOP_INITVAL 0x128
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#define QSERDES_V8_USB43_COM_INTEGLOOP_EN 0x12c
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#define QSERDES_V8_USB43_COM_INTEGLOOP_P_PATH_GAIN0 0x130
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#define QSERDES_V8_USB43_COM_INTEGLOOP_P_PATH_GAIN1 0x134
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#define QSERDES_V8_USB43_COM_VCOCAL_DEADMAN_CTRL 0x138
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#define QSERDES_V8_USB43_COM_VCO_TUNE_CTRL 0x13c
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#define QSERDES_V8_USB43_COM_VCO_TUNE_MAP 0x140
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#define QSERDES_V8_USB43_COM_VCO_TUNE_INITVAL1 0x144
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#define QSERDES_V8_USB43_COM_VCO_TUNE_INITVAL2 0x148
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#define QSERDES_V8_USB43_COM_VCO_TUNE_MINVAL1 0x14c
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#define QSERDES_V8_USB43_COM_VCO_TUNE_MINVAL2 0x150
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#define QSERDES_V8_USB43_COM_VCO_TUNE_MAXVAL1 0x154
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#define QSERDES_V8_USB43_COM_VCO_TUNE_MAXVAL2 0x158
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#define QSERDES_V8_USB43_COM_VCO_TUNE_TIMER1 0x15c
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#define QSERDES_V8_USB43_COM_VCO_TUNE_TIMER2 0x160
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#define QSERDES_V8_USB43_COM_CLK_SELECT 0x164
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#define QSERDES_V8_USB43_COM_PLL_ANALOG 0x168
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#define QSERDES_V8_USB43_COM_SW_RESET 0x16c
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#define QSERDES_V8_USB43_COM_CORE_CLK_EN 0x170
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#define QSERDES_V8_USB43_COM_CMN_CONFIG_1 0x174
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#define QSERDES_V8_USB43_COM_CMN_CONFIG_3 0x178
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#define QSERDES_V8_USB43_COM_CMN_RATE_OVERRIDE 0x17c
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#define QSERDES_V8_USB43_COM_SVS_MODE_CLK_SEL 0x180
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#define QSERDES_V8_USB43_COM_DEBUG_BUS_SEL 0x184
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#define QSERDES_V8_USB43_COM_CMN_MISC1 0x188
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#define QSERDES_V8_USB43_COM_CMN_MODE 0x18c
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#define QSERDES_V8_USB43_COM_CMN_MODE_CONTD 0x190
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#define QSERDES_V8_USB43_COM_CMN_MODE_CONTD1 0x194
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#define QSERDES_V8_USB43_COM_CMN_MODE_CONTD2 0x198
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#define QSERDES_V8_USB43_COM_VCO_DC_LEVEL_CTRL 0x19c
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#define QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1 0x1a0
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#define QSERDES_V8_USB43_COM_ADDITIONAL_CTRL_1 0x1a4
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#define QSERDES_V8_USB43_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a8
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#define QSERDES_V8_USB43_COM_AUTO_GAIN_ADJ_CTRL_2 0x1ac
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#define QSERDES_V8_USB43_COM_AUTO_GAIN_ADJ_CTRL_3 0x1b0
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#define QSERDES_V8_USB43_COM_AUTO_GAIN_ADJ_CTRL_4 0x1b4
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#define QSERDES_V8_USB43_COM_ADDITIONAL_MISC 0x1b8
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#define QSERDES_V8_USB43_COM_ADDITIONAL_MISC_2 0x1bc
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#define QSERDES_V8_USB43_COM_ADDITIONAL_MISC_3 0x1c0
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#define QSERDES_V8_USB43_COM_ADDITIONAL_MISC_4 0x1c4
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#define QSERDES_V8_USB43_COM_ADDITIONAL_MISC_5 0x1c8
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#define QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE2 0x1cc
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#define QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE2 0x1d0
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#define QSERDES_V8_USB43_COM_SSC_STEP_SIZE3_MODE2 0x1d4
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#define QSERDES_V8_USB43_COM_CLK_EP_DIV_MODE2 0x1d8
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#define QSERDES_V8_USB43_COM_CP_CTRL_MODE2 0x1dc
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#define QSERDES_V8_USB43_COM_PLL_RCTRL_MODE2 0x1e0
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#define QSERDES_V8_USB43_COM_PLL_CCTRL_MODE2 0x1e4
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#define QSERDES_V8_USB43_COM_CORECLK_DIV_MODE2 0x1e8
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#define QSERDES_V8_USB43_COM_LOCK_CMP1_MODE2 0x1ec
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#define QSERDES_V8_USB43_COM_LOCK_CMP2_MODE2 0x1f0
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#define QSERDES_V8_USB43_COM_DEC_START_MODE2 0x1f4
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#define QSERDES_V8_USB43_COM_DEC_START_MSB_MODE2 0x1f8
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#define QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE2 0x1fc
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#define QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE2 0x200
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#define QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE2 0x204
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#define QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE2 0x208
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#define QSERDES_V8_USB43_COM_INTEGLOOP_GAIN1_MODE2 0x20c
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#define QSERDES_V8_USB43_COM_VCO_TUNE1_MODE2 0x210
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#define QSERDES_V8_USB43_COM_VCO_TUNE2_MODE2 0x214
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#define QSERDES_V8_USB43_COM_PLL_IVCO_MODE2 0x218
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#define QSERDES_V8_USB43_COM_HSCLK_SEL_2 0x21c
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#define QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE2 0x220
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#define QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE2 0x224
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#define QSERDES_V8_USB43_COM_HSCLK_HS_SWITCH_SEL_2 0x228
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#define QSERDES_V8_USB43_COM_CMN_CONFIG_2 0x22c
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#define QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_2 0x230
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#define QSERDES_V8_USB43_COM_IVCOCAL_CONFIG_0 0x234
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#define QSERDES_V8_USB43_COM_IVCOCAL_CONFIG_1 0x238
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#define QSERDES_V8_USB43_COM_IVCOCAL_CONFIG_2 0x23c
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#define QSERDES_V8_USB43_COM_IVCOCAL_CONFIG_3 0x240
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#define QSERDES_V8_USB43_COM_IVCOCAL_CONFIG_4 0x244
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#define QSERDES_V8_USB43_COM_IVCOCAL_CONFIG_5 0x248
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#define QSERDES_V8_USB43_COM_LOCK_CMP1_EARLY_MODE0 0x24c
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#define QSERDES_V8_USB43_COM_LOCK_CMP2_EARLY_MODE0 0x250
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#define QSERDES_V8_USB43_COM_LOCK_CMP1_EARLY_MODE1 0x254
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#define QSERDES_V8_USB43_COM_LOCK_CMP2_EARLY_MODE1 0x258
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#define QSERDES_V8_USB43_COM_LOCK_CMP1_EARLY_MODE2 0x25c
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#define QSERDES_V8_USB43_COM_LOCK_CMP2_EARLY_MODE2 0x260
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#define QSERDES_V8_USB43_COM_EARLY_LOCK_CONFIG_0 0x264
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#define QSERDES_V8_USB43_COM_EARLY_LOCK_CONFIG_1 0x268
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#define QSERDES_V8_USB43_COM_ADAPTIVE_ANALOG_CONFIG 0x26c
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#define QSERDES_V8_USB43_COM_CP_CTRL_ADAPTIVE_MODE0 0x270
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#define QSERDES_V8_USB43_COM_PLL_RCCTRL_ADAPTIVE_MODE0 0x274
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#define QSERDES_V8_USB43_COM_PLL_CCTRL_ADAPTIVE_MODE0 0x278
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#define QSERDES_V8_USB43_COM_CP_CTRL_ADAPTIVE_MODE1 0x27c
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#define QSERDES_V8_USB43_COM_PLL_RCCTRL_ADAPTIVE_MODE1 0x280
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#define QSERDES_V8_USB43_COM_PLL_CCTRL_ADAPTIVE_MODE1 0x284
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#define QSERDES_V8_USB43_COM_CP_CTRL_ADAPTIVE_MODE2 0x288
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#define QSERDES_V8_USB43_COM_PLL_RCCTRL_ADAPTIVE_MODE2 0x28c
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#define QSERDES_V8_USB43_COM_PLL_CCTRL_ADAPTIVE_MODE2 0x290
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#define QSERDES_V8_USB43_COM_CMN_MODE_CONTD3 0x294
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#define QSERDES_V8_USB43_COM_CMN_MODE_CONTD4 0x298
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#define QSERDES_V8_USB43_COM_CMN_MODE_CONTD5 0x29c
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#define QSERDES_V8_USB43_COM_CMN_MODE_CONTD6 0x2a0
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#define QSERDES_V8_USB43_COM_ADDITIONAL_MISC_6 0x2a4
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#define QSERDES_V8_USB43_COM_ADDITIONAL_MISC_7 0x2a8
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#define QSERDES_V8_USB43_COM_VCO_WAIT_CYCLES 0x2ac
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#define QSERDES_V8_USB43_COM_BIAS_WAIT_CYCLES 0x2b0
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#define QSERDES_V8_USB43_COM_AUX_CLK_PSM_ENABLE 0x2b4
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#define QSERDES_V8_USB43_COM_PLL_SPARE_FOR_ECO 0x2b8
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#define QSERDES_V8_USB43_COM_PLL_SPARE_FOR_ECO_1 0x2bc
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#define QSERDES_V8_USB43_COM_PLL_SPARE_FOR_ECO_2 0x2c0
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#define QSERDES_V8_USB43_COM_LDO_CAL_1 0x2c4
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#define QSERDES_V8_USB43_COM_LDO_CAL_2 0x2c8
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#define QSERDES_V8_USB43_COM_LDO_CAL_3 0x2cc
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#define QSERDES_V8_USB43_COM_LDO_CAL_4 0x2d0
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#define QSERDES_V8_USB43_COM_LDO_CAL_5 0x2d4
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#define QSERDES_V8_USB43_COM_DCC_CAL_1 0x2d8
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#define QSERDES_V8_USB43_COM_DCC_CAL_2 0x2dc
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#define QSERDES_V8_USB43_COM_DCC_CAL_3 0x2e0
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#define QSERDES_V8_USB43_COM_DCC_CAL_4 0x2e4
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#define QSERDES_V8_USB43_COM_DCC_CAL_5 0x2e8
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#define QSERDES_V8_USB43_COM_DCC_CAL_6 0x2ec
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#define QSERDES_V8_USB43_COM_PSM_CAL_EN 0x2f0
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#define QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1 0x2f4
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#define QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_2 0x2f8
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#define QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL 0x2fc
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#define QSERDES_V8_USB43_COM_DCC_CAL_7 0x300
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#define QSERDES_V8_USB43_COM_DCC_CAL_8 0x304
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#define QSERDES_V8_USB43_COM_DCC_CAL_9 0x308
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#define QSERDES_V8_USB43_COM_MODE_OPERATION_STATUS 0x30c
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#define QSERDES_V8_USB43_COM_SYSCLK_DET_COMP_STATUS 0x310
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#define QSERDES_V8_USB43_COM_CMN_STATUS 0x314
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#define QSERDES_V8_USB43_COM_RESET_SM_STATUS 0x318
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#define QSERDES_V8_USB43_COM_RESTRIM_CODE_STATUS 0x31c
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#define QSERDES_V8_USB43_COM_PLLCAL_CODE1_STATUS 0x320
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#define QSERDES_V8_USB43_COM_PLLCAL_CODE2_STATUS 0x324
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#define QSERDES_V8_USB43_COM_INTEGLOOP_BINCODE_STATUS 0x328
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#define QSERDES_V8_USB43_COM_DEBUG_BUS0 0x32c
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#define QSERDES_V8_USB43_COM_DEBUG_BUS1 0x330
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#define QSERDES_V8_USB43_COM_DEBUG_BUS2 0x334
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#define QSERDES_V8_USB43_COM_DEBUG_BUS3 0x338
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#define QSERDES_V8_USB43_COM_C_READY_STATUS 0x33c
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#define QSERDES_V8_USB43_COM_READ_DUMMY_1 0x340
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#define QSERDES_V8_USB43_COM_READ_DUMMY_2 0x344
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#define QSERDES_V8_USB43_COM_READ_DUMMY_3 0x348
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#define QSERDES_V8_USB43_COM_IVCO_CAL_CODE_STATUS 0x34c
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#define QSERDES_V8_USB43_COM_PLL_LDO_CAL_STATUS_2 0x350
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#define QSERDES_V8_USB43_COM_PLL_LDO_CAL_STATUS_3 0x354
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#endif
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