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Starting with Glymur, the PCIe and DP PHYs qserdes register offsets differ for the same version number. So in order to be able to differentiate between them, add these ones with DP prefix. Add the necessary PHY setting tables for enabling the DP path within the QMP subsystem. Introduced some new callbacks for v8 specific sequences, such as for clock configurations based on the different link speeds. Wesley Cheng added some updated settings from the hardware programming guides on existing PHY tables and clock settings. Co-developed-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://patch.msgid.link/20251209-linux-next-12825-v8-9-42133596bda0@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
25 lines
850 B
C
25 lines
850 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_DP_PHY_V8_H_
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#define QCOM_PHY_QMP_DP_PHY_V8_H_
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/* Only for QMP V8 PHY - DP PHY registers */
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#define QSERDES_V8_DP_PHY_VCO_DIV 0x070
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#define QSERDES_V8_DP_PHY_AUX_INTERRUPT_STATUS 0x0e0
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#define QSERDES_V8_DP_PHY_TSYNC_OVRD 0x074
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#define QSERDES_V8_DP_PHY_TX0_TX1_LANE_CTL 0x078
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#define QSERDES_V8_DP_PHY_TX2_TX3_LANE_CTL 0x0bc
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#define QSERDES_V8_DP_PHY_AUXLESS_CFG1 0x0c8
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#define QSERDES_V8_DP_PHY_LFPS_PERIOD 0x0d0
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#define QSERDES_V8_DP_PHY_LFPS_CYC 0x0d4
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#define QSERDES_V8_DP_PHY_AUXLESS_SETUP_CYC 0x0d8
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#define QSERDES_V8_DP_PHY_AUXLESS_SILENCE_CYC 0x0d8
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#define QSERDES_V8_DP_PHY_LN0_DRV_LVL 0x0e0
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#define QSERDES_V8_DP_PHY_LN1_DRV_LVL 0x0e4
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#define QSERDES_V8_DP_PHY_STATUS 0x114
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#endif
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