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The Glymur platform is the first one to use the eDP PHY version 8. This makes it incompatible with any of the earlier platforms and therefore requires a dedicated compatible. So document it. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20251224-phy-qcom-edp-add-glymur-support-v6-1-4fcba75a6fa9@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
115 lines
2.2 KiB
YAML
115 lines
2.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/qcom,edp-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm eDP PHY
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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description:
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The Qualcomm eDP PHY is found in a number of Qualcomm platform and provides
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the physical interface for Embedded Display Port.
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properties:
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compatible:
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oneOf:
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- enum:
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- qcom,glymur-dp-phy
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- qcom,sa8775p-edp-phy
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- qcom,sc7280-edp-phy
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- qcom,sc8180x-edp-phy
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- qcom,sc8280xp-dp-phy
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- qcom,sc8280xp-edp-phy
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- qcom,x1e80100-dp-phy
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- items:
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- enum:
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- qcom,qcs8300-edp-phy
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- const: qcom,sa8775p-edp-phy
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reg:
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items:
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- description: PHY base register block
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- description: tx0 register block
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- description: tx1 register block
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- description: PLL register block
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clocks:
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minItems: 2
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maxItems: 3
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clock-names:
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minItems: 2
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items:
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- const: aux
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- const: cfg_ahb
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- const: ref
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"#clock-cells":
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const: 1
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"#phy-cells":
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const: 0
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power-domains:
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maxItems: 1
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vdda-phy-supply: true
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vdda-pll-supply: true
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- "#clock-cells"
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- "#phy-cells"
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allOf:
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- if:
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properties:
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compatible:
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enum:
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- qcom,glymur-dp-phy
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- qcom,x1e80100-dp-phy
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then:
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properties:
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clocks:
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minItems: 3
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maxItems: 3
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clock-names:
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minItems: 3
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maxItems: 3
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else:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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minItems: 2
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maxItems: 2
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additionalProperties: false
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examples:
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- |
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phy@aec2a00 {
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compatible = "qcom,sc8180x-edp-phy";
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reg = <0x0aec2a00 0x1c0>,
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<0x0aec2200 0xa0>,
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<0x0aec2600 0xa0>,
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<0x0aec2000 0x19c>;
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clocks = <&dispcc 0>, <&dispcc 1>;
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clock-names = "aux", "cfg_ahb";
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#clock-cells = <1>;
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#phy-cells = <0>;
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vdda-phy-supply = <&vdd_a_edp_0_1p2>;
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vdda-pll-supply = <&vdd_a_edp_0_0p9>;
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};
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...
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