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1aa82181a3
When an application issues a query IOCTL while auto suspend is running,
a deadlock can occur. The query path holds dev_lock and then calls
pm_runtime_resume_and_get(), which waits for the ongoing suspend to
complete. Meanwhile, the suspend callback attempts to acquire dev_lock
and blocks, resulting in a deadlock.
Fix this by releasing dev_lock before calling pm_runtime_resume_and_get()
and reacquiring it after the call completes. Also acquire dev_lock in the
resume callback to keep the locking consistent.
Fixes: 063db45183 ("accel/amdxdna: Enhance runtime power management")
Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>
Signed-off-by: Lizhi Hou <lizhi.hou@amd.com>
Link: https://patch.msgid.link/20260211204644.722758-1-lizhi.hou@amd.com
126 lines
2.5 KiB
C
126 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2024, Advanced Micro Devices, Inc.
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*/
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#include <drm/amdxdna_accel.h>
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#include <drm/drm_device.h>
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#include <drm/drm_print.h>
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#include <drm/gpu_scheduler.h>
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#include "aie2_pci.h"
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#include "amdxdna_pci_drv.h"
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#include "amdxdna_pm.h"
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#define AIE2_CLK_GATING_ENABLE 1
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#define AIE2_CLK_GATING_DISABLE 0
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static int aie2_pm_set_clk_gating(struct amdxdna_dev_hdl *ndev, u32 val)
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{
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int ret;
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ret = aie2_runtime_cfg(ndev, AIE2_RT_CFG_CLK_GATING, &val);
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if (ret)
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return ret;
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ndev->clk_gating = val;
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return 0;
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}
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int aie2_pm_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
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{
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int ret;
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ret = amdxdna_pm_resume_get_locked(ndev->xdna);
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if (ret)
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return ret;
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ret = ndev->priv->hw_ops.set_dpm(ndev, dpm_level);
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if (!ret)
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ndev->dpm_level = dpm_level;
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amdxdna_pm_suspend_put(ndev->xdna);
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return ret;
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}
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int aie2_pm_init(struct amdxdna_dev_hdl *ndev)
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{
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int ret;
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if (ndev->dev_status != AIE2_DEV_UNINIT) {
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/* Resume device */
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ret = ndev->priv->hw_ops.set_dpm(ndev, ndev->dpm_level);
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if (ret)
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return ret;
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ret = aie2_pm_set_clk_gating(ndev, ndev->clk_gating);
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if (ret)
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return ret;
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return 0;
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}
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while (ndev->priv->dpm_clk_tbl[ndev->max_dpm_level].hclk)
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ndev->max_dpm_level++;
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ndev->max_dpm_level--;
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ret = ndev->priv->hw_ops.set_dpm(ndev, ndev->max_dpm_level);
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if (ret)
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return ret;
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ndev->dpm_level = ndev->max_dpm_level;
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ret = aie2_pm_set_clk_gating(ndev, AIE2_CLK_GATING_ENABLE);
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if (ret)
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return ret;
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ndev->pw_mode = POWER_MODE_DEFAULT;
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ndev->dft_dpm_level = ndev->max_dpm_level;
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return 0;
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}
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int aie2_pm_set_mode(struct amdxdna_dev_hdl *ndev, enum amdxdna_power_mode_type target)
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{
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struct amdxdna_dev *xdna = ndev->xdna;
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u32 clk_gating, dpm_level;
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int ret;
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drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
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if (ndev->pw_mode == target)
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return 0;
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switch (target) {
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case POWER_MODE_TURBO:
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if (ndev->hwctx_num) {
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XDNA_ERR(xdna, "Can not set turbo when there is active hwctx");
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return -EINVAL;
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}
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clk_gating = AIE2_CLK_GATING_DISABLE;
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dpm_level = ndev->max_dpm_level;
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break;
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case POWER_MODE_HIGH:
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clk_gating = AIE2_CLK_GATING_ENABLE;
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dpm_level = ndev->max_dpm_level;
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break;
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case POWER_MODE_DEFAULT:
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clk_gating = AIE2_CLK_GATING_ENABLE;
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dpm_level = ndev->dft_dpm_level;
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break;
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default:
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return -EOPNOTSUPP;
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}
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ret = aie2_pm_set_dpm(ndev, dpm_level);
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if (ret)
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return ret;
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ret = aie2_pm_set_clk_gating(ndev, clk_gating);
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if (ret)
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return ret;
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ndev->pw_mode = target;
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return 0;
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}
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