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fc17de9901
Call kvm_wait_lapic_expire() when POSTED_INTR_ON is set and the vector for LVTT is set in PIR before TD entry. KVM always assumes a timer IRQ was injected if APIC state is protected. For TDX guest, APIC state is protected and KVM injects timer IRQ via posted interrupt. To avoid unnecessary wait calls, only call kvm_wait_lapic_expire() when a timer IRQ was injected, i.e., POSTED_INTR_ON is set and the vector for LVTT is set in PIR. Add a helper to test PIR. Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> Co-developed-by: Binbin Wu <binbin.wu@linux.intel.com> Signed-off-by: Binbin Wu <binbin.wu@linux.intel.com> Message-ID: <20250222014757.897978-7-binbin.wu@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
123 lines
3 KiB
C
123 lines
3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _X86_POSTED_INTR_H
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#define _X86_POSTED_INTR_H
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#include <asm/irq_vectors.h>
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#define POSTED_INTR_ON 0
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#define POSTED_INTR_SN 1
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#define PID_TABLE_ENTRY_VALID 1
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/* Posted-Interrupt Descriptor */
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struct pi_desc {
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union {
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u32 pir[8]; /* Posted interrupt requested */
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u64 pir64[4];
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};
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union {
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struct {
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u16 notifications; /* Suppress and outstanding bits */
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u8 nv;
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u8 rsvd_2;
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u32 ndst;
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};
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u64 control;
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};
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u32 rsvd[6];
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} __aligned(64);
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static inline bool pi_test_and_set_on(struct pi_desc *pi_desc)
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{
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return test_and_set_bit(POSTED_INTR_ON, (unsigned long *)&pi_desc->control);
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}
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static inline bool pi_test_and_clear_on(struct pi_desc *pi_desc)
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{
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return test_and_clear_bit(POSTED_INTR_ON, (unsigned long *)&pi_desc->control);
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}
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static inline bool pi_test_and_clear_sn(struct pi_desc *pi_desc)
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{
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return test_and_clear_bit(POSTED_INTR_SN, (unsigned long *)&pi_desc->control);
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}
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static inline bool pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
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{
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return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
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}
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static inline bool pi_is_pir_empty(struct pi_desc *pi_desc)
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{
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return bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS);
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}
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static inline void pi_set_sn(struct pi_desc *pi_desc)
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{
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set_bit(POSTED_INTR_SN, (unsigned long *)&pi_desc->control);
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}
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static inline void pi_set_on(struct pi_desc *pi_desc)
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{
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set_bit(POSTED_INTR_ON, (unsigned long *)&pi_desc->control);
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}
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static inline void pi_clear_on(struct pi_desc *pi_desc)
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{
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clear_bit(POSTED_INTR_ON, (unsigned long *)&pi_desc->control);
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}
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static inline void pi_clear_sn(struct pi_desc *pi_desc)
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{
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clear_bit(POSTED_INTR_SN, (unsigned long *)&pi_desc->control);
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}
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static inline bool pi_test_on(struct pi_desc *pi_desc)
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{
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return test_bit(POSTED_INTR_ON, (unsigned long *)&pi_desc->control);
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}
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static inline bool pi_test_sn(struct pi_desc *pi_desc)
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{
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return test_bit(POSTED_INTR_SN, (unsigned long *)&pi_desc->control);
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}
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static inline bool pi_test_pir(int vector, struct pi_desc *pi_desc)
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{
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return test_bit(vector, (unsigned long *)pi_desc->pir);
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}
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/* Non-atomic helpers */
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static inline void __pi_set_sn(struct pi_desc *pi_desc)
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{
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pi_desc->notifications |= BIT(POSTED_INTR_SN);
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}
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static inline void __pi_clear_sn(struct pi_desc *pi_desc)
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{
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pi_desc->notifications &= ~BIT(POSTED_INTR_SN);
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}
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#ifdef CONFIG_X86_POSTED_MSI
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/*
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* Not all external vectors are subject to interrupt remapping, e.g. IOMMU's
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* own interrupts. Here we do not distinguish them since those vector bits in
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* PIR will always be zero.
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*/
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static inline bool pi_pending_this_cpu(unsigned int vector)
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{
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struct pi_desc *pid = this_cpu_ptr(&posted_msi_pi_desc);
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if (WARN_ON_ONCE(vector > NR_VECTORS || vector < FIRST_EXTERNAL_VECTOR))
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return false;
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return test_bit(vector, (unsigned long *)pid->pir);
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}
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extern void intel_posted_msi_init(void);
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#else
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static inline bool pi_pending_this_cpu(unsigned int vector) { return false; }
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static inline void intel_posted_msi_init(void) {};
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#endif /* X86_POSTED_MSI */
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#endif /* _X86_POSTED_INTR_H */
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