mirror of
https://github.com/torvalds/linux.git
synced 2026-03-08 01:24:47 +01:00
c303e8b86d
Document Microchip LAN969x MIIM compatible. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251229184004.571837-11-robert.marko@sartura.hr Signed-off-by: Jakub Kicinski <kuba@kernel.org>
76 lines
1.4 KiB
YAML
76 lines
1.4 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/net/mscc,miim.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Microsemi MII Management Controller (MIIM)
|
|
|
|
maintainers:
|
|
- Alexandre Belloni <alexandre.belloni@bootlin.com>
|
|
|
|
allOf:
|
|
- $ref: mdio.yaml#
|
|
|
|
properties:
|
|
compatible:
|
|
oneOf:
|
|
- enum:
|
|
- mscc,ocelot-miim
|
|
- microchip,lan966x-miim
|
|
- items:
|
|
- enum:
|
|
- microchip,lan9691-miim
|
|
- const: mscc,ocelot-miim
|
|
|
|
"#address-cells":
|
|
const: 1
|
|
|
|
"#size-cells":
|
|
const: 0
|
|
|
|
reg:
|
|
items:
|
|
- description: base address
|
|
- description: associated reset register for internal PHYs
|
|
minItems: 1
|
|
|
|
interrupts:
|
|
maxItems: 1
|
|
|
|
clocks:
|
|
maxItems: 1
|
|
|
|
clock-frequency: true
|
|
|
|
resets:
|
|
items:
|
|
- description:
|
|
Reset shared with all blocks attached to the Switch Core Register
|
|
Bus (CSR) including VRAP slave.
|
|
|
|
reset-names:
|
|
items:
|
|
- const: switch
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- "#address-cells"
|
|
- "#size-cells"
|
|
|
|
unevaluatedProperties: false
|
|
|
|
examples:
|
|
- |
|
|
mdio@107009c {
|
|
compatible = "mscc,ocelot-miim";
|
|
reg = <0x107009c 0x36>, <0x10700f0 0x8>;
|
|
interrupts = <14>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
phy0: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|