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Document the device tree bindings for the DWC3 USB controller found in Google Tensor SoCs, starting with the G5 generation (codename: laguna). The Tensor G5 silicon represents a complete architectural departure from previous generations (like gs101), including entirely new clock/reset schemes, top-level wrapper and register interface. Consequently, existing Samsung/Exynos DWC3 USB bindings are incompatible, necessitating this new device tree binding. The USB controller on Tensor G5 is based on Synopsys DWC3 IP and features Dual-Role Device single port with hibernation support. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Roy Luo <royluo@google.com> Link: https://patch.msgid.link/20251218-controller-v10-1-4047c9077274@google.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
140 lines
4.1 KiB
YAML
140 lines
4.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright (c) 2025, Google LLC
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/usb/google,lga-dwc3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Google Tensor Series G5 (Laguna) DWC3 USB SoC Controller
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maintainers:
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- Roy Luo <royluo@google.com>
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description:
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Describes the DWC3 USB controller block implemented on Google Tensor SoCs,
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starting with the G5 generation (laguna). Based on Synopsys DWC3 IP, the
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controller features Dual-Role Device single port with hibernation add-on.
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properties:
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compatible:
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const: google,lga-dwc3
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reg:
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items:
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- description: Core DWC3 IP registers.
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interrupts:
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items:
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- description: Core DWC3 interrupt.
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- description: High speed power management event for remote wakeup.
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- description: Super speed power management event for remote wakeup.
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interrupt-names:
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items:
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- const: core
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- const: hs_pme
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- const: ss_pme
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clocks:
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items:
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- description: Non-sticky module clock.
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- description: Sticky module clock.
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clock-names:
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items:
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- const: non_sticky
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- const: sticky
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resets:
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items:
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- description: Non-sticky module reset.
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- description: Sticky module reset.
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- description: DRD bus reset.
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- description: Top-level reset.
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reset-names:
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items:
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- const: non_sticky
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- const: sticky
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- const: drd_bus
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- const: top
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power-domains:
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items:
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- description: Power switchable domain, the child of top domain.
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Turning it on puts the controller into full power state,
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turning it off puts the controller into power gated state.
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- description: Top domain, the parent of power switchable domain.
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Turning it on puts the controller into power gated state,
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turning it off completely shuts off the controller.
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power-domain-names:
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items:
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- const: psw
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- const: top
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iommus:
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maxItems: 1
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google,usb-cfg-csr:
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description:
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A phandle to a syscon node used to access the USB configuration
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registers. These registers are the top-level wrapper of the USB
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subsystem and provide control and status for the integrated USB
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controller and USB PHY.
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: phandle to the syscon node.
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- description: USB host controller configuration register offset.
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- description: USB custom interrrupts control register offset.
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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- clocks
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- clock-names
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- resets
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- reset-names
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- power-domains
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- power-domain-names
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- google,usb-cfg-csr
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allOf:
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- $ref: snps,dwc3-common.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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usb@c400000 {
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compatible = "google,lga-dwc3";
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reg = <0 0x0c400000 0 0xd060>;
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interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "core", "hs_pme", "ss_pme";
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clocks = <&hsion_usbc_non_sticky_clk>, <&hsion_usbc_sticky_clk>;
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clock-names = "non_sticky", "sticky";
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resets = <&hsion_resets_usbc_non_sticky>, <&hsion_resets_usbc_sticky>,
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<&hsion_resets_usb_drd_bus>, <&hsion_resets_usb_top>;
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reset-names = "non_sticky", "sticky", "drd_bus", "top";
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power-domains = <&hsio_n_usb_psw>, <&hsio_n_usb>;
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power-domain-names = "psw", "top";
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phys = <&usb_phy 0>;
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phy-names = "usb2-phy";
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snps,quirk-frame-length-adjustment = <0x20>;
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snps,gfladj-refclk-lpm-sel-quirk;
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snps,incr-burst-type-adjustment = <4>;
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google,usb-cfg-csr = <&usb_cfg_csr 0x0 0x20>;
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};
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};
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...
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