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da1682d5e8
This patch adds the functions/controls to support the calibration. The mixer controls could trigger a calibration and load temperature/r0 value. Signed-off-by: Shuming Fan <shumingf@realtek.com> Link: https://patch.msgid.link/20251216090616.3955293-1-shumingf@realtek.com Signed-off-by: Mark Brown <broonie@kernel.org>
179 lines
4.4 KiB
C
179 lines
4.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* rt1320-sdw.h -- RT1320 SDCA ALSA SoC audio driver header
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*
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* Copyright(c) 2024 Realtek Semiconductor Corp.
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*/
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#ifndef __RT1320_SDW_H__
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#define __RT1320_SDW_H__
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#include <linux/regmap.h>
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#include <linux/soundwire/sdw.h>
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#include <linux/soundwire/sdw_type.h>
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#include <linux/soundwire/sdw_registers.h>
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#include <sound/soc.h>
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#include "../../../drivers/soundwire/bus.h"
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#define RT1320_DEV_ID 0x6981
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#define RT1321_DEV_ID 0x7045
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/* imp-defined registers */
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#define RT1320_DEV_VERSION_ID_1 0xc404
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#define RT1320_DEV_ID_1 0xc405
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#define RT1320_DEV_ID_0 0xc406
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#define RT1320_POWER_STATE 0xc560
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#define RT1321_PATCH_MAIN_VER 0x1000cffe
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#define RT1321_PATCH_BETA_VER 0x1000cfff
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#define RT1320_KR0_STATUS_CNT 0x1000f008
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#define RT1320_KR0_INT_READY 0x1000f021
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#define RT1320_HIFI_VER_0 0x3fe2e000
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#define RT1320_HIFI_VER_1 0x3fe2e001
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#define RT1320_HIFI_VER_2 0x3fe2e002
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#define RT1320_HIFI_VER_3 0x3fe2e003
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/* RT1320 SDCA Control - function number */
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#define FUNC_NUM_AMP 0x04
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#define FUNC_NUM_MIC 0x02
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/* RT1320 SDCA entity */
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#define RT1320_SDCA_ENT0 0x00
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#define RT1320_SDCA_ENT_PDE11 0x2a
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#define RT1320_SDCA_ENT_PDE23 0x33
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#define RT1320_SDCA_ENT_PDE27 0x27
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#define RT1320_SDCA_ENT_FU14 0x32
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#define RT1320_SDCA_ENT_FU21 0x03
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#define RT1320_SDCA_ENT_FU113 0x30
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#define RT1320_SDCA_ENT_CS14 0x13
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#define RT1320_SDCA_ENT_CS21 0x21
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#define RT1320_SDCA_ENT_CS113 0x12
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#define RT1320_SDCA_ENT_SAPU 0x29
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#define RT1320_SDCA_ENT_PPU21 0x04
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/* RT1320 SDCA control */
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#define RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX 0x10
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#define RT1320_SDCA_CTL_REQ_POWER_STATE 0x01
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#define RT1320_SDCA_CTL_ACTUAL_POWER_STATE 0x10
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#define RT1320_SDCA_CTL_FU_MUTE 0x01
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#define RT1320_SDCA_CTL_FU_VOLUME 0x02
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#define RT1320_SDCA_CTL_SAPU_PROTECTION_MODE 0x10
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#define RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS 0x11
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#define RT1320_SDCA_CTL_POSTURE_NUMBER 0x10
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#define RT1320_SDCA_CTL_FUNC_STATUS 0x10
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/* RT1320 SDCA channel */
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#define CH_01 0x01
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#define CH_02 0x02
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/* Function_Status */
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#define FUNCTION_NEEDS_INITIALIZATION BIT(5)
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/* Sample Frequency Index */
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#define RT1320_SDCA_RATE_16000HZ 0x04
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#define RT1320_SDCA_RATE_32000HZ 0x07
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#define RT1320_SDCA_RATE_44100HZ 0x08
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#define RT1320_SDCA_RATE_48000HZ 0x09
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#define RT1320_SDCA_RATE_96000HZ 0x0b
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#define RT1320_SDCA_RATE_192000HZ 0x0d
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enum {
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RT1320_AIF1,
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RT1320_AIF2,
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};
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/*
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* The version id will be useful to distinguish the capability between the different IC versions.
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* Currently, VA and VB have different DSP FW versions.
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*/
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enum rt1320_version_id {
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RT1320_VA,
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RT1320_VB,
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RT1320_VC,
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};
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#define RT1320_VER_B_ID 0x07392238
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#define RT1320_VAB_MCU_PATCH "realtek/rt1320/rt1320-patch-code-vab.bin"
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#define RT1320_VC_MCU_PATCH "realtek/rt1320/rt1320-patch-code-vc.bin"
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#define RT1321_VA_MCU_PATCH "realtek/rt1320/rt1321-patch-code-va.bin"
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#define RT1320_FW_PARAM_ADDR 0x3fc2ab80
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#define RT1320_CMD_ID 0x3fc2ab81
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#define RT1320_CMD_PARAM_ADDR 0x3fc2ab90
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#define RT1320_DSPFW_STATUS_ADDR 0x3fc2bfc4
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#define RT1321_FW_PARAM_ADDR 0x3fc2d300
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#define RT1321_CMD_ID 0x3fc2d301
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#define RT1321_CMD_PARAM_ADDR 0x3fc2d310
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#define RT1321_DSPFW_STATUS_ADDR 0x3fc2dfc4
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/* FW parameter id 6, 7 */
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struct rt1320_datafixpoint {
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int silencedetect;
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int r0;
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int meanr0;
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int advancegain;
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int ts;
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int re;
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int t;
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int invrs;
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};
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struct rt1320_paramcmd {
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unsigned char moudleid;
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unsigned char commandtype;
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unsigned short reserved1;
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unsigned int commandlength;
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long long reserved2;
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unsigned int paramid;
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unsigned int paramlength;
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};
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enum rt1320_fw_cmdid {
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RT1320_FW_READY,
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RT1320_SET_PARAM,
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RT1320_GET_PARAM,
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RT1320_GET_POOLSIZE,
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};
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enum rt1320_power_state {
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RT1320_NORMAL_STATE = 0x18,
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RT1320_K_R0_STATE = 0x1b,
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};
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enum rt1320_rw_type {
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RT1320_BRA_WRITE = 0,
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RT1320_BRA_READ = 1,
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RT1320_PARAM_WRITE = 2,
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RT1320_PARAM_READ = 3,
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};
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struct rt1320_sdw_priv {
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struct snd_soc_component *component;
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struct regmap *regmap;
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struct regmap *mbq_regmap;
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struct sdw_slave *sdw_slave;
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struct sdw_bus_params params;
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bool hw_init;
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bool first_hw_init;
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int version_id;
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unsigned int dev_id;
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bool fu_dapm_mute;
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bool fu_mixer_mute[4];
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unsigned long long r0_l_reg;
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unsigned long long r0_r_reg;
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unsigned int r0_l_calib;
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unsigned int r0_r_calib;
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unsigned int temp_l_calib;
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unsigned int temp_r_calib;
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const char *dspfw_name;
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bool cali_done;
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bool fw_load_done;
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bool rae_update_done;
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struct work_struct load_dspfw_work;
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struct sdw_bpt_msg bra_msg;
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};
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#endif /* __RT1320_SDW_H__ */
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