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3974a585be
The SPI core provides the default of_node for the controller, inherited from the actual (parent) device. No need to repeat it in the driver. Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: William Zhang <william.zhang@broadcom.com> Acked-by: Chen-Yu Tsai <wens@kernel.org> # sun4i, sun6i Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260112203534.4186261-3-andriy.shevchenko@linux.intel.com Tested-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
99 lines
2.3 KiB
C
99 lines
2.3 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2011, 2012 Cavium, Inc.
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*/
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <asm/octeon/octeon.h>
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#include "spi-cavium.h"
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static int octeon_spi_probe(struct platform_device *pdev)
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{
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void __iomem *reg_base;
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struct spi_controller *host;
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struct octeon_spi *p;
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int err = -ENOENT;
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host = spi_alloc_host(&pdev->dev, sizeof(struct octeon_spi));
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if (!host)
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return -ENOMEM;
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p = spi_controller_get_devdata(host);
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platform_set_drvdata(pdev, host);
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reg_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(reg_base)) {
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err = PTR_ERR(reg_base);
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goto fail;
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}
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p->register_base = reg_base;
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p->sys_freq = octeon_get_io_clock_rate();
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p->regs.config = 0;
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p->regs.status = 0x08;
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p->regs.tx = 0x10;
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p->regs.data = 0x80;
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host->num_chipselect = 4;
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host->mode_bits = SPI_CPHA |
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SPI_CPOL |
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SPI_CS_HIGH |
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SPI_LSB_FIRST |
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SPI_3WIRE;
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host->transfer_one_message = octeon_spi_transfer_one_message;
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host->bits_per_word_mask = SPI_BPW_MASK(8);
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host->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
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err = devm_spi_register_controller(&pdev->dev, host);
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if (err) {
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dev_err(&pdev->dev, "register host failed: %d\n", err);
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goto fail;
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}
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dev_info(&pdev->dev, "OCTEON SPI bus driver\n");
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return 0;
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fail:
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spi_controller_put(host);
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return err;
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}
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static void octeon_spi_remove(struct platform_device *pdev)
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{
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struct spi_controller *host = platform_get_drvdata(pdev);
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struct octeon_spi *p = spi_controller_get_devdata(host);
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/* Clear the CSENA* and put everything in a known state. */
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writeq(0, p->register_base + OCTEON_SPI_CFG(p));
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}
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static const struct of_device_id octeon_spi_match[] = {
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{ .compatible = "cavium,octeon-3010-spi", },
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{},
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};
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MODULE_DEVICE_TABLE(of, octeon_spi_match);
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static struct platform_driver octeon_spi_driver = {
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.driver = {
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.name = "spi-octeon",
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.of_match_table = octeon_spi_match,
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},
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.probe = octeon_spi_probe,
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.remove = octeon_spi_remove,
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};
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module_platform_driver(octeon_spi_driver);
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MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver");
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MODULE_AUTHOR("David Daney");
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MODULE_LICENSE("GPL");
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