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02cf3710c5
Add register sequences for PCIe + XAUI multilink configuration for 100MHz reference clock. The register sequences are fetched from a table by indexing entries based on unique 'keys' generated by the Bitwise OR defined below: REFCLK0_RATE | REFCLK1_RATE | LINK0_TYPE | LINK1_TYPE | SSC_TYPE As of now, LINK_TYPE is a 3-bit value corresponding to the PHY type. With the introduction of TYPE_XAUI, we need a 4-bit value to represent the LINK_TYPE as TYPE_XAUI has the numerical value 8. Hence, extend the LINKx_MASK macros to 4-bit masks. While at it, extend REFCLKx_MASK macros as well to 4-bit masks to support reference clock frequencies that will be added in the future. Adjust the 'LINKx_SHIFT' and the 'REFCLKx_SHIFT' macros to account for the aforementioned changes made to the masks. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> [s-vadapalli: elaborated on changes made to macros in the commit message] Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20260112054636.108027-3-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org> |
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| .. | ||
| cdns-dphy-rx.c | ||
| cdns-dphy.c | ||
| Kconfig | ||
| Makefile | ||
| phy-cadence-salvo.c | ||
| phy-cadence-sierra.c | ||
| phy-cadence-torrent.c | ||