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147792c395
When both eth interfaces with links up are added to a bridge or hsr
interface, ping fails if the link speed is not 1Gbps (e.g., 100Mbps).
The issue is seen because when switching to offload (bridge/hsr) mode,
prueth_emac_restart() restarts the firmware and clears DRAM with
memset_io(), setting all memory to 0. This includes PORT_LINK_SPEED_OFFSET
which firmware reads for link speed. The value 0 corresponds to
FW_LINK_SPEED_1G (0x00), so for 1Gbps links the default value is correct
and ping works. For 100Mbps links, the firmware needs FW_LINK_SPEED_100M
(0x01) but gets 0 instead, causing ping to fail. The function
emac_adjust_link() is called to reconfigure, but it detects no state change
(emac->link is still 1, speed/duplex match PHY) so new_state remains false
and icssg_config_set_speed() is never called to correct the firmware speed
value.
The fix resets emac->link to 0 before calling emac_adjust_link() in
prueth_emac_common_start(). This forces new_state=true, ensuring
icssg_config_set_speed() is called to write the correct speed value to
firmware memory.
Fixes:
|
||
|---|---|---|
| .. | ||
| icssg | ||
| icssm | ||
| am65-cpsw-ethtool.c | ||
| am65-cpsw-nuss.c | ||
| am65-cpsw-nuss.h | ||
| am65-cpsw-qos.c | ||
| am65-cpsw-qos.h | ||
| am65-cpsw-switchdev.c | ||
| am65-cpsw-switchdev.h | ||
| am65-cpts.c | ||
| am65-cpts.h | ||
| cpsw-common.c | ||
| cpsw-phy-sel.c | ||
| cpsw.c | ||
| cpsw.h | ||
| cpsw_ale.c | ||
| cpsw_ale.h | ||
| cpsw_ethtool.c | ||
| cpsw_new.c | ||
| cpsw_priv.c | ||
| cpsw_priv.h | ||
| cpsw_sl.c | ||
| cpsw_sl.h | ||
| cpsw_switchdev.c | ||
| cpsw_switchdev.h | ||
| cpts.c | ||
| cpts.h | ||
| davinci_cpdma.c | ||
| davinci_cpdma.h | ||
| davinci_emac.c | ||
| davinci_mdio.c | ||
| k3-cppi-desc-pool.c | ||
| k3-cppi-desc-pool.h | ||
| Kconfig | ||
| Makefile | ||
| netcp.h | ||
| netcp_core.c | ||
| netcp_ethss.c | ||
| netcp_sgmii.c | ||
| netcp_xgbepcsr.c | ||
| tlan.c | ||
| tlan.h | ||