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The ROHM BD72720 is a power management IC which continues the BD71828 family of PMICs. Similarly to the BD71815 and BD71828, the BD72720 integrates regulators, charger, RTC, clock gate and GPIOs. The main difference to the earlier PMICs is that the BD72720 has two different I2C slave addresses. In addition to the registers behind the 'main I2C address', most of the charger (and to some extent LED) control is done via registers behind a 'secondary I2C slave address', 0x4c. Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com> Link: https://patch.msgid.link/c7b3f1b25616a0add21cea38019e50a89873b6ac.1765804226.git.mazziesaccount@gmail.com Signed-off-by: Lee Jones <lee@kernel.org>
1084 lines
47 KiB
C
1084 lines
47 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2019 ROHM Semiconductors
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*
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* ROHM BD718[15/28/79] and BD72720 PMIC driver
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*/
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#include <linux/gpio_keys.h>
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#include <linux/i2c.h>
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#include <linux/input.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/rohm-bd71815.h>
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#include <linux/mfd/rohm-bd71828.h>
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#include <linux/mfd/rohm-bd72720.h>
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#include <linux/mfd/rohm-generic.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <linux/types.h>
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#define BD72720_TYPED_IRQ_REG(_irq, _stat_offset, _mask, _type_offset) \
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[_irq] = { \
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.reg_offset = (_stat_offset), \
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.mask = (_mask), \
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{ \
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.type_reg_offset = (_type_offset), \
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.type_reg_mask = BD72720_GPIO_IRQ_TYPE_MASK, \
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.type_rising_val = BD72720_GPIO_IRQ_TYPE_RISING, \
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.type_falling_val = BD72720_GPIO_IRQ_TYPE_FALLING, \
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.type_level_low_val = BD72720_GPIO_IRQ_TYPE_LOW, \
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.type_level_high_val = BD72720_GPIO_IRQ_TYPE_HIGH, \
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.types_supported = IRQ_TYPE_EDGE_BOTH | \
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IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW, \
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}, \
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}
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static struct gpio_keys_button button = {
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.code = KEY_POWER,
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.gpio = -1,
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.type = EV_KEY,
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};
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static const struct gpio_keys_platform_data bd71828_powerkey_data = {
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.buttons = &button,
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.nbuttons = 1,
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.name = "bd71828-pwrkey",
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};
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static const struct resource bd71815_rtc_irqs[] = {
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DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC0, "bd70528-rtc-alm-0"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC1, "bd70528-rtc-alm-1"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC2, "bd70528-rtc-alm-2"),
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};
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static const struct resource bd71828_rtc_irqs[] = {
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DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC0, "bd70528-rtc-alm-0"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC1, "bd70528-rtc-alm-1"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC2, "bd70528-rtc-alm-2"),
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};
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static const struct resource bd72720_rtc_irqs[] = {
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DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC0, "bd70528-rtc-alm-0"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC1, "bd70528-rtc-alm-1"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC2, "bd70528-rtc-alm-2"),
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};
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static const struct resource bd71815_power_irqs[] = {
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DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_RMV, "bd71815-dcin-rmv"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_OUT, "bd71815-dcin-clps-out"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_IN, "bd71815-dcin-clps-in"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_RES, "bd71815-dcin-ovp-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_DET, "bd71815-dcin-ovp-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_RES, "bd71815-dcin-mon-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_DET, "bd71815-dcin-mon-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_RES, "bd71815-vsys-uv-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_DET, "bd71815-vsys-uv-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_RES, "bd71815-vsys-low-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_DET, "bd71815-vsys-low-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_RES, "bd71815-vsys-mon-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_DET, "bd71815-vsys-mon-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TEMP, "bd71815-chg-wdg-temp"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TIME, "bd71815-chg-wdg"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_RES, "bd71815-rechg-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_DET, "bd71815-rechg-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, "bd71815-ranged-temp-transit"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_STATE_TRANSITION, "bd71815-chg-state-change"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_NORMAL, "bd71815-bat-temp-normal"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_ERANGE, "bd71815-bat-temp-erange"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_REMOVED, "bd71815-bat-rmv"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DETECTED, "bd71815-bat-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_REMOVED, "bd71815-therm-rmv"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_DETECTED, "bd71815-therm-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DEAD, "bd71815-bat-dead"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_RES, "bd71815-bat-short-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_DET, "bd71815-bat-short-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_RES, "bd71815-bat-low-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_DET, "bd71815-bat-low-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_RES, "bd71815-bat-over-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_DET, "bd71815-bat-over-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_RES, "bd71815-bat-mon-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_DET, "bd71815-bat-mon-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON1, "bd71815-bat-cc-mon1"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON2, "bd71815-bat-cc-mon2"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON3, "bd71815-bat-cc-mon3"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_RES, "bd71815-bat-oc1-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_DET, "bd71815-bat-oc1-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_RES, "bd71815-bat-oc2-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_DET, "bd71815-bat-oc2-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_RES, "bd71815-bat-oc3-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_DET, "bd71815-bat-oc3-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_RES, "bd71815-temp-bat-low-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_DET, "bd71815-temp-bat-low-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_RES, "bd71815-temp-bat-hi-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_DET, "bd71815-temp-bat-hi-det"),
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};
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static const struct mfd_cell bd71815_mfd_cells[] = {
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{ .name = "bd71815-pmic", },
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{ .name = "bd71815-clk", },
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{ .name = "bd71815-gpo", },
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{
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.name = "bd71815-power",
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.num_resources = ARRAY_SIZE(bd71815_power_irqs),
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.resources = &bd71815_power_irqs[0],
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},
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{
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.name = "bd71815-rtc",
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.num_resources = ARRAY_SIZE(bd71815_rtc_irqs),
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.resources = &bd71815_rtc_irqs[0],
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},
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};
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static const struct resource bd71828_power_irqs[] = {
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DEFINE_RES_IRQ_NAMED(BD71828_INT_CHG_TOPOFF_TO_DONE,
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"bd71828-chg-done"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_DCIN_DET, "bd71828-pwr-dcin-in"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_DCIN_RMV, "bd71828-pwr-dcin-out"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_BAT_LOW_VOLT_RES,
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"bd71828-vbat-normal"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_BAT_LOW_VOLT_DET, "bd71828-vbat-low"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_HI_DET, "bd71828-btemp-hi"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_HI_RES, "bd71828-btemp-cool"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_LOW_DET, "bd71828-btemp-lo"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_LOW_RES,
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"bd71828-btemp-warm"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_VF_DET,
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"bd71828-temp-hi"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_VF_RES,
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"bd71828-temp-norm"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_125_DET,
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"bd71828-temp-125-over"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_125_RES,
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"bd71828-temp-125-under"),
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};
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static struct mfd_cell bd71828_mfd_cells[] = {
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{ .name = "bd71828-pmic", },
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{ .name = "bd71828-gpio", },
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{ .name = "bd71828-led", .of_compatible = "rohm,bd71828-leds" },
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/*
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* We use BD71837 driver to drive the clock block. Only differences to
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* BD70528 clock gate are the register address and mask.
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*/
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{ .name = "bd71828-clk", },
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{
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.name = "bd71828-power",
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.resources = bd71828_power_irqs,
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.num_resources = ARRAY_SIZE(bd71828_power_irqs),
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}, {
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.name = "bd71828-rtc",
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.resources = bd71828_rtc_irqs,
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.num_resources = ARRAY_SIZE(bd71828_rtc_irqs),
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}, {
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.name = "gpio-keys",
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.platform_data = &bd71828_powerkey_data,
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.pdata_size = sizeof(bd71828_powerkey_data),
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},
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};
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static const struct resource bd72720_power_irqs[] = {
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DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_RMV, "bd72720_int_vbus_rmv"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_DET, "bd72720_int_vbus_det"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_MON_RES, "bd72720_int_vbus_mon_res"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_MON_DET, "bd72720_int_vbus_mon_det"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_MON_RES, "bd72720_int_vsys_mon_res"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_MON_DET, "bd72720_int_vsys_mon_det"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_UV_RES, "bd72720_int_vsys_uv_res"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_UV_DET, "bd72720_int_vsys_uv_det"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_LO_RES, "bd72720_int_vsys_lo_res"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_LO_DET, "bd72720_int_vsys_lo_det"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_OV_RES, "bd72720_int_vsys_ov_res"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_OV_DET, "bd72720_int_vsys_ov_det"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_ILIM, "bd72720_int_bat_ilim"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_DONE, "bd72720_int_chg_done"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_EXTEMP_TOUT, "bd72720_int_extemp_tout"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_WDT_EXP, "bd72720_int_chg_wdt_exp"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_MNT_OUT, "bd72720_int_bat_mnt_out"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_MNT_IN, "bd72720_int_bat_mnt_in"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_TRNS, "bd72720_int_chg_trns"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_MON_RES, "bd72720_int_vbat_mon_res"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_MON_DET, "bd72720_int_vbat_mon_det"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_SHT_RES, "bd72720_int_vbat_sht_res"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_SHT_DET, "bd72720_int_vbat_sht_det"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_LO_RES, "bd72720_int_vbat_lo_res"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_LO_DET, "bd72720_int_vbat_lo_det"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_OV_RES, "bd72720_int_vbat_ov_res"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_OV_DET, "bd72720_int_vbat_ov_det"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_RMV, "bd72720_int_bat_rmv"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_DET, "bd72720_int_bat_det"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_DBAT_DET, "bd72720_int_dbat_det"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_TEMP_TRNS, "bd72720_int_bat_temp_trns"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_LOBTMP_RES, "bd72720_int_lobtmp_res"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_LOBTMP_DET, "bd72720_int_lobtmp_det"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_OVBTMP_RES, "bd72720_int_ovbtmp_res"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_OVBTMP_DET, "bd72720_int_ovbtmp_det"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR1_RES, "bd72720_int_ocur1_res"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR1_DET, "bd72720_int_ocur1_det"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR2_RES, "bd72720_int_ocur2_res"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR2_DET, "bd72720_int_ocur2_det"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR3_RES, "bd72720_int_ocur3_res"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR3_DET, "bd72720_int_ocur3_det"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON1_DET, "bd72720_int_cc_mon1_det"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON2_DET, "bd72720_int_cc_mon2_det"),
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DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON3_DET, "bd72720_int_cc_mon3_det"),
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};
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static const struct mfd_cell bd72720_mfd_cells[] = {
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{ .name = "bd72720-pmic", },
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{ .name = "bd72720-gpio", },
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{ .name = "bd72720-led", },
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{ .name = "bd72720-clk", },
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{
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.name = "bd72720-power",
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.resources = bd72720_power_irqs,
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.num_resources = ARRAY_SIZE(bd72720_power_irqs),
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}, {
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.name = "bd72720-rtc",
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.resources = bd72720_rtc_irqs,
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.num_resources = ARRAY_SIZE(bd72720_rtc_irqs),
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}, {
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.name = "gpio-keys",
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.platform_data = &bd71828_powerkey_data,
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.pdata_size = sizeof(bd71828_powerkey_data),
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},
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};
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static const struct regmap_range bd71815_volatile_ranges[] = {
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regmap_reg_range(BD71815_REG_SEC, BD71815_REG_YEAR),
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regmap_reg_range(BD71815_REG_CONF, BD71815_REG_BAT_TEMP),
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regmap_reg_range(BD71815_REG_VM_IBAT_U, BD71815_REG_CC_CTRL),
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regmap_reg_range(BD71815_REG_CC_STAT, BD71815_REG_CC_CURCD_L),
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regmap_reg_range(BD71815_REG_VM_BTMP_MON, BD71815_REG_VM_BTMP_MON),
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regmap_reg_range(BD71815_REG_INT_STAT, BD71815_REG_INT_UPDATE),
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regmap_reg_range(BD71815_REG_VM_VSYS_U, BD71815_REG_REX_CTRL_1),
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regmap_reg_range(BD71815_REG_FULL_CCNTD_3, BD71815_REG_CCNTD_CHG_2),
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};
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static const struct regmap_range bd71828_volatile_ranges[] = {
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regmap_reg_range(BD71828_REG_PS_CTRL_1, BD71828_REG_PS_CTRL_1),
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regmap_reg_range(BD71828_REG_PS_CTRL_3, BD71828_REG_PS_CTRL_3),
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regmap_reg_range(BD71828_REG_RTC_SEC, BD71828_REG_RTC_YEAR),
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/*
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* For now make all charger registers volatile because many
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* needs to be and because the charger block is not that
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* performance critical.
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*/
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regmap_reg_range(BD71828_REG_CHG_STATE, BD71828_REG_CHG_FULL),
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regmap_reg_range(BD71828_REG_INT_MAIN, BD71828_REG_IO_STAT),
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};
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static const struct regmap_range bd72720_volatile_ranges_4b[] = {
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regmap_reg_range(BD72720_REG_RESETSRC_1, BD72720_REG_RESETSRC_2),
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regmap_reg_range(BD72720_REG_POWER_STATE, BD72720_REG_POWER_STATE),
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/* The state indicator bit changes when new state is reached */
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regmap_reg_range(BD72720_REG_PS_CTRL_1, BD72720_REG_PS_CTRL_1),
|
|
regmap_reg_range(BD72720_REG_RCVNUM, BD72720_REG_RCVNUM),
|
|
regmap_reg_range(BD72720_REG_CONF, BD72720_REG_HALL_STAT),
|
|
regmap_reg_range(BD72720_REG_RTC_SEC, BD72720_REG_RTC_YEAR),
|
|
regmap_reg_range(BD72720_REG_INT_LVL1_STAT, BD72720_REG_INT_ETC2_SRC),
|
|
};
|
|
|
|
static const struct regmap_range bd72720_precious_ranges_4b[] = {
|
|
regmap_reg_range(BD72720_REG_INT_LVL1_STAT, BD72720_REG_INT_ETC2_STAT),
|
|
};
|
|
|
|
/*
|
|
* The BD72720 is an odd beast in that it contains two separate sets of
|
|
* registers, both starting from address 0x0. The twist is that these "pages"
|
|
* are behind different I2C slave addresses. Most of the registers are behind
|
|
* a slave address 0x4b, which will be used as the "main" address for this
|
|
* device.
|
|
*
|
|
* Most of the charger related registers are located behind slave address 0x4c.
|
|
* It is tempting to push the dealing with the charger registers and the extra
|
|
* 0x4c device in power-supply driver - but perhaps it's better for the sake of
|
|
* the cleaner re-use to deal with setting up all of the regmaps here.
|
|
* Furthermore, the LED stuff may need access to both of these devices.
|
|
*
|
|
* Instead of providing one of the regmaps to sub-devices in MFD platform data,
|
|
* we create one more 'wrapper regmap' with custom read/write operations. These
|
|
* custom accessors will select which of the 'real' regmaps to use, based on
|
|
* the register address.
|
|
*
|
|
* The register addresses are 8-bit, so we add offset 0x100 to the addresses
|
|
* behind the secondary slave 0x4c. The 'wrapper' regmap can then detect the
|
|
* correct slave address based on the register address and call regmap_write()
|
|
* and regmap_read() using correct 'real' regmap. This way the registers of
|
|
* both of the slaves can be accessed using one 'wrapper' regmap.
|
|
*
|
|
* NOTE: The added offsets mean that the defined addresses for slave 0x4c must
|
|
* be used through the 'wrapper' regmap because the offset must be stripped
|
|
* from the register addresses. The 0x4b can be accessed both indirectly using
|
|
* the 'wrapper' regmap, and directly using the 'real' regmap.
|
|
*/
|
|
#define BD72720_SECONDARY_I2C_SLAVE 0x4c
|
|
#define BD72720_SECONDARY_I2C_REG_OFFSET 0x100
|
|
|
|
struct bd72720_regmaps {
|
|
struct regmap *map1_4b;
|
|
struct regmap *map2_4c;
|
|
};
|
|
|
|
/* Translate the slave 0x4c wrapper register address to a real one */
|
|
#define BD72720_REG_UNWRAP(reg) ((reg) - BD72720_SECONDARY_I2C_REG_OFFSET)
|
|
|
|
/* Ranges given to 'real' 0x4c regmap must use unwrapped addresses. */
|
|
#define BD72720_UNWRAP_REG_RANGE(startreg, endreg) \
|
|
regmap_reg_range(BD72720_REG_UNWRAP(startreg), BD72720_REG_UNWRAP(endreg))
|
|
|
|
static const struct regmap_range bd72720_volatile_ranges_4c[] = {
|
|
/* Status information */
|
|
BD72720_UNWRAP_REG_RANGE(BD72720_REG_CHG_STATE, BD72720_REG_CHG_EN),
|
|
/*
|
|
* Under certain circumstances, write to some bits may be
|
|
* ignored
|
|
*/
|
|
BD72720_UNWRAP_REG_RANGE(BD72720_REG_CHG_CTRL, BD72720_REG_CHG_CTRL),
|
|
/*
|
|
* TODO: Ensure this is used to advertise state, not (only?) to
|
|
* control it.
|
|
*/
|
|
BD72720_UNWRAP_REG_RANGE(BD72720_REG_VSYS_STATE_STAT, BD72720_REG_VSYS_STATE_STAT),
|
|
/* Measured data */
|
|
BD72720_UNWRAP_REG_RANGE(BD72720_REG_VM_VBAT_U, BD72720_REG_VM_VF_L),
|
|
/* Self clearing bits */
|
|
BD72720_UNWRAP_REG_RANGE(BD72720_REG_VM_VSYS_SA_MINMAX_CTRL,
|
|
BD72720_REG_VM_VSYS_SA_MINMAX_CTRL),
|
|
/* Counters, self clearing bits */
|
|
BD72720_UNWRAP_REG_RANGE(BD72720_REG_CC_CURCD_U, BD72720_REG_CC_CTRL),
|
|
/* Self clearing bits */
|
|
BD72720_UNWRAP_REG_RANGE(BD72720_REG_CC_CCNTD_CTRL, BD72720_REG_CC_CCNTD_CTRL),
|
|
/* Self clearing bits */
|
|
BD72720_UNWRAP_REG_RANGE(BD72720_REG_IMPCHK_CTRL, BD72720_REG_IMPCHK_CTRL),
|
|
};
|
|
|
|
static const struct regmap_access_table bd71815_volatile_regs = {
|
|
.yes_ranges = &bd71815_volatile_ranges[0],
|
|
.n_yes_ranges = ARRAY_SIZE(bd71815_volatile_ranges),
|
|
};
|
|
|
|
static const struct regmap_access_table bd71828_volatile_regs = {
|
|
.yes_ranges = &bd71828_volatile_ranges[0],
|
|
.n_yes_ranges = ARRAY_SIZE(bd71828_volatile_ranges),
|
|
};
|
|
|
|
static const struct regmap_access_table bd72720_volatile_regs_4b = {
|
|
.yes_ranges = &bd72720_volatile_ranges_4b[0],
|
|
.n_yes_ranges = ARRAY_SIZE(bd72720_volatile_ranges_4b),
|
|
};
|
|
|
|
static const struct regmap_access_table bd72720_precious_regs_4b = {
|
|
.yes_ranges = &bd72720_precious_ranges_4b[0],
|
|
.n_yes_ranges = ARRAY_SIZE(bd72720_precious_ranges_4b),
|
|
};
|
|
|
|
static const struct regmap_access_table bd72720_volatile_regs_4c = {
|
|
.yes_ranges = &bd72720_volatile_ranges_4c[0],
|
|
.n_yes_ranges = ARRAY_SIZE(bd72720_volatile_ranges_4c),
|
|
};
|
|
|
|
static const struct regmap_config bd71815_regmap = {
|
|
.reg_bits = 8,
|
|
.val_bits = 8,
|
|
.volatile_table = &bd71815_volatile_regs,
|
|
.max_register = BD71815_MAX_REGISTER - 1,
|
|
.cache_type = REGCACHE_MAPLE,
|
|
};
|
|
|
|
static const struct regmap_config bd71828_regmap = {
|
|
.reg_bits = 8,
|
|
.val_bits = 8,
|
|
.volatile_table = &bd71828_volatile_regs,
|
|
.max_register = BD71828_MAX_REGISTER,
|
|
.cache_type = REGCACHE_MAPLE,
|
|
};
|
|
|
|
static int regmap_write_wrapper(void *context, unsigned int reg, unsigned int val)
|
|
{
|
|
struct bd72720_regmaps *maps = context;
|
|
|
|
if (reg < BD72720_SECONDARY_I2C_REG_OFFSET)
|
|
return regmap_write(maps->map1_4b, reg, val);
|
|
|
|
reg = BD72720_REG_UNWRAP(reg);
|
|
|
|
return regmap_write(maps->map2_4c, reg, val);
|
|
}
|
|
|
|
static int regmap_read_wrapper(void *context, unsigned int reg, unsigned int *val)
|
|
{
|
|
struct bd72720_regmaps *maps = context;
|
|
|
|
if (reg < BD72720_SECONDARY_I2C_REG_OFFSET)
|
|
return regmap_read(maps->map1_4b, reg, val);
|
|
|
|
reg = BD72720_REG_UNWRAP(reg);
|
|
|
|
return regmap_read(maps->map2_4c, reg, val);
|
|
}
|
|
|
|
static const struct regmap_config bd72720_wrapper_map_config = {
|
|
.name = "wrap-map",
|
|
.reg_bits = 9,
|
|
.val_bits = 8,
|
|
.max_register = BD72720_REG_IMPCHK_CTRL,
|
|
/*
|
|
* We don't want to duplicate caches. It would be a bit faster to
|
|
* have the cache in this 'wrapper regmap', and not in the 'real
|
|
* regmaps' bd72720_regmap_4b and bd72720_regmap_4c below. This would
|
|
* require all the subdevices to use the wrapper-map in order to be
|
|
* able to benefit from the cache.
|
|
* Currently most of the sub-devices use only the same slave-address
|
|
* as this MFD driver. Now, because we don't add the offset to the
|
|
* registers belonging to this slave, those devices can use either the
|
|
* wrapper map, or the bd72720_regmap_4b directly. This means majority
|
|
* of our sub devices don't need to care which regmap they get using
|
|
* the dev_get_regmap(). This unifies the code between the BD72720 and
|
|
* those variants which don't have this 'multiple slave addresses'
|
|
* -hassle.
|
|
* So, for a small performance penalty, we simplify the code for the
|
|
* sub-devices by having the caches in the wrapped regmaps and not here.
|
|
*/
|
|
.cache_type = REGCACHE_NONE,
|
|
.reg_write = regmap_write_wrapper,
|
|
.reg_read = regmap_read_wrapper,
|
|
};
|
|
|
|
static const struct regmap_config bd72720_regmap_4b = {
|
|
.reg_bits = 8,
|
|
.val_bits = 8,
|
|
.volatile_table = &bd72720_volatile_regs_4b,
|
|
.precious_table = &bd72720_precious_regs_4b,
|
|
.max_register = BD72720_REG_INT_ETC2_SRC,
|
|
.cache_type = REGCACHE_MAPLE,
|
|
};
|
|
|
|
static const struct regmap_config bd72720_regmap_4c = {
|
|
.reg_bits = 8,
|
|
.val_bits = 8,
|
|
.volatile_table = &bd72720_volatile_regs_4c,
|
|
.max_register = BD72720_REG_UNWRAP(BD72720_REG_IMPCHK_CTRL),
|
|
.cache_type = REGCACHE_MAPLE,
|
|
};
|
|
|
|
/*
|
|
* Mapping of main IRQ register bits to sub-IRQ register offsets so that we can
|
|
* access corect sub-IRQ registers based on bits that are set in main IRQ
|
|
* register. BD71815 and BD71828 have same sub-register-block offests, the
|
|
* BD72720 has a different one.
|
|
*/
|
|
|
|
static unsigned int bit0_offsets[] = {11}; /* RTC IRQ */
|
|
static unsigned int bit1_offsets[] = {10}; /* TEMP IRQ */
|
|
static unsigned int bit2_offsets[] = {6, 7, 8, 9}; /* BAT MON IRQ */
|
|
static unsigned int bit3_offsets[] = {5}; /* BAT IRQ */
|
|
static unsigned int bit4_offsets[] = {4}; /* CHG IRQ */
|
|
static unsigned int bit5_offsets[] = {3}; /* VSYS IRQ */
|
|
static unsigned int bit6_offsets[] = {1, 2}; /* DCIN IRQ */
|
|
static unsigned int bit7_offsets[] = {0}; /* BUCK IRQ */
|
|
|
|
static unsigned int bd72720_bit0_offsets[] = {0, 1}; /* PS1 and PS2 */
|
|
static unsigned int bd72720_bit1_offsets[] = {2, 3}; /* DVS1 and DVS2 */
|
|
static unsigned int bd72720_bit2_offsets[] = {4}; /* VBUS */
|
|
static unsigned int bd72720_bit3_offsets[] = {5}; /* VSYS */
|
|
static unsigned int bd72720_bit4_offsets[] = {6}; /* CHG */
|
|
static unsigned int bd72720_bit5_offsets[] = {7, 8}; /* BAT1 and BAT2 */
|
|
static unsigned int bd72720_bit6_offsets[] = {9}; /* IBAT */
|
|
static unsigned int bd72720_bit7_offsets[] = {10, 11}; /* ETC1 and ETC2 */
|
|
|
|
static const struct regmap_irq_sub_irq_map bd718xx_sub_irq_offsets[] = {
|
|
REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets),
|
|
REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets),
|
|
REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets),
|
|
REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets),
|
|
REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets),
|
|
REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets),
|
|
REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets),
|
|
REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets),
|
|
};
|
|
|
|
static const struct regmap_irq_sub_irq_map bd72720_sub_irq_offsets[] = {
|
|
REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit0_offsets),
|
|
REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit1_offsets),
|
|
REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit2_offsets),
|
|
REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit3_offsets),
|
|
REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit4_offsets),
|
|
REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit5_offsets),
|
|
REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit6_offsets),
|
|
REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit7_offsets),
|
|
};
|
|
|
|
static const struct regmap_irq bd71815_irqs[] = {
|
|
REGMAP_IRQ_REG(BD71815_INT_BUCK1_OCP, 0, BD71815_INT_BUCK1_OCP_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_BUCK2_OCP, 0, BD71815_INT_BUCK2_OCP_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_BUCK3_OCP, 0, BD71815_INT_BUCK3_OCP_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_BUCK4_OCP, 0, BD71815_INT_BUCK4_OCP_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_BUCK5_OCP, 0, BD71815_INT_BUCK5_OCP_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_LED_OVP, 0, BD71815_INT_LED_OVP_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_LED_OCP, 0, BD71815_INT_LED_OCP_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_LED_SCP, 0, BD71815_INT_LED_SCP_MASK),
|
|
/* DCIN1 interrupts */
|
|
REGMAP_IRQ_REG(BD71815_INT_DCIN_RMV, 1, BD71815_INT_DCIN_RMV_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_CLPS_OUT, 1, BD71815_INT_CLPS_OUT_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_CLPS_IN, 1, BD71815_INT_CLPS_IN_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_RES, 1, BD71815_INT_DCIN_OVP_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_DET, 1, BD71815_INT_DCIN_OVP_DET_MASK),
|
|
/* DCIN2 interrupts */
|
|
REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_RES, 2, BD71815_INT_DCIN_MON_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_DET, 2, BD71815_INT_DCIN_MON_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_WDOG, 2, BD71815_INT_WDOG_MASK),
|
|
/* Vsys */
|
|
REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_RES, 3, BD71815_INT_VSYS_UV_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_DET, 3, BD71815_INT_VSYS_UV_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_RES, 3, BD71815_INT_VSYS_LOW_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_DET, 3, BD71815_INT_VSYS_LOW_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_RES, 3, BD71815_INT_VSYS_MON_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_DET, 3, BD71815_INT_VSYS_MON_DET_MASK),
|
|
/* Charger */
|
|
REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TEMP, 4, BD71815_INT_CHG_WDG_TEMP_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TIME, 4, BD71815_INT_CHG_WDG_TIME_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_RES, 4, BD71815_INT_CHG_RECHARGE_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_DET, 4, BD71815_INT_CHG_RECHARGE_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, 4,
|
|
BD71815_INT_CHG_RANGED_TEMP_TRANSITION_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_CHG_STATE_TRANSITION, 4, BD71815_INT_CHG_STATE_TRANSITION_MASK),
|
|
/* Battery */
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_NORMAL, 5, BD71815_INT_BAT_TEMP_NORMAL_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_ERANGE, 5, BD71815_INT_BAT_TEMP_ERANGE_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_REMOVED, 5, BD71815_INT_BAT_REMOVED_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_DETECTED, 5, BD71815_INT_BAT_DETECTED_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_THERM_REMOVED, 5, BD71815_INT_THERM_REMOVED_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_THERM_DETECTED, 5, BD71815_INT_THERM_DETECTED_MASK),
|
|
/* Battery Mon 1 */
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_DEAD, 6, BD71815_INT_BAT_DEAD_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_RES, 6, BD71815_INT_BAT_SHORTC_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_DET, 6, BD71815_INT_BAT_SHORTC_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_RES, 6, BD71815_INT_BAT_LOW_VOLT_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_DET, 6, BD71815_INT_BAT_LOW_VOLT_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_RES, 6, BD71815_INT_BAT_OVER_VOLT_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_DET, 6, BD71815_INT_BAT_OVER_VOLT_DET_MASK),
|
|
/* Battery Mon 2 */
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_MON_RES, 7, BD71815_INT_BAT_MON_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_MON_DET, 7, BD71815_INT_BAT_MON_DET_MASK),
|
|
/* Battery Mon 3 (Coulomb counter) */
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON1, 8, BD71815_INT_BAT_CC_MON1_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON2, 8, BD71815_INT_BAT_CC_MON2_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON3, 8, BD71815_INT_BAT_CC_MON3_MASK),
|
|
/* Battery Mon 4 */
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_RES, 9, BD71815_INT_BAT_OVER_CURR_1_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_DET, 9, BD71815_INT_BAT_OVER_CURR_1_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_RES, 9, BD71815_INT_BAT_OVER_CURR_2_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_DET, 9, BD71815_INT_BAT_OVER_CURR_2_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_RES, 9, BD71815_INT_BAT_OVER_CURR_3_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_DET, 9, BD71815_INT_BAT_OVER_CURR_3_DET_MASK),
|
|
/* Temperature */
|
|
REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_RES, 10, BD71815_INT_TEMP_BAT_LOW_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_DET, 10, BD71815_INT_TEMP_BAT_LOW_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_RES, 10, BD71815_INT_TEMP_BAT_HI_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_DET, 10, BD71815_INT_TEMP_BAT_HI_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_RES, 10,
|
|
BD71815_INT_TEMP_CHIP_OVER_125_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_DET, 10,
|
|
BD71815_INT_TEMP_CHIP_OVER_125_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_RES, 10,
|
|
BD71815_INT_TEMP_CHIP_OVER_VF_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_DET, 10,
|
|
BD71815_INT_TEMP_CHIP_OVER_VF_DET_MASK),
|
|
/* RTC Alarm */
|
|
REGMAP_IRQ_REG(BD71815_INT_RTC0, 11, BD71815_INT_RTC0_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_RTC1, 11, BD71815_INT_RTC1_MASK),
|
|
REGMAP_IRQ_REG(BD71815_INT_RTC2, 11, BD71815_INT_RTC2_MASK),
|
|
};
|
|
|
|
static const struct regmap_irq bd71828_irqs[] = {
|
|
REGMAP_IRQ_REG(BD71828_INT_BUCK1_OCP, 0, BD71828_INT_BUCK1_OCP_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BUCK2_OCP, 0, BD71828_INT_BUCK2_OCP_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BUCK3_OCP, 0, BD71828_INT_BUCK3_OCP_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BUCK4_OCP, 0, BD71828_INT_BUCK4_OCP_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BUCK5_OCP, 0, BD71828_INT_BUCK5_OCP_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BUCK6_OCP, 0, BD71828_INT_BUCK6_OCP_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BUCK7_OCP, 0, BD71828_INT_BUCK7_OCP_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_PGFAULT, 0, BD71828_INT_PGFAULT_MASK),
|
|
/* DCIN1 interrupts */
|
|
REGMAP_IRQ_REG(BD71828_INT_DCIN_DET, 1, BD71828_INT_DCIN_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_DCIN_RMV, 1, BD71828_INT_DCIN_RMV_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_CLPS_OUT, 1, BD71828_INT_CLPS_OUT_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_CLPS_IN, 1, BD71828_INT_CLPS_IN_MASK),
|
|
/* DCIN2 interrupts */
|
|
REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_RES, 2, BD71828_INT_DCIN_MON_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_DET, 2, BD71828_INT_DCIN_MON_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_LONGPUSH, 2, BD71828_INT_LONGPUSH_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_MIDPUSH, 2, BD71828_INT_MIDPUSH_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_SHORTPUSH, 2, BD71828_INT_SHORTPUSH_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_PUSH, 2, BD71828_INT_PUSH_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_WDOG, 2, BD71828_INT_WDOG_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_SWRESET, 2, BD71828_INT_SWRESET_MASK),
|
|
/* Vsys */
|
|
REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_RES, 3, BD71828_INT_VSYS_UV_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_DET, 3, BD71828_INT_VSYS_UV_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_RES, 3, BD71828_INT_VSYS_LOW_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_DET, 3, BD71828_INT_VSYS_LOW_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_IN, 3, BD71828_INT_VSYS_HALL_IN_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_TOGGLE, 3, BD71828_INT_VSYS_HALL_TOGGLE_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_RES, 3, BD71828_INT_VSYS_MON_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_DET, 3, BD71828_INT_VSYS_MON_DET_MASK),
|
|
/* Charger */
|
|
REGMAP_IRQ_REG(BD71828_INT_CHG_DCIN_ILIM, 4, BD71828_INT_CHG_DCIN_ILIM_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_CHG_TOPOFF_TO_DONE, 4, BD71828_INT_CHG_TOPOFF_TO_DONE_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TEMP, 4, BD71828_INT_CHG_WDG_TEMP_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TIME, 4, BD71828_INT_CHG_WDG_TIME_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_RES, 4, BD71828_INT_CHG_RECHARGE_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_DET, 4, BD71828_INT_CHG_RECHARGE_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_CHG_RANGED_TEMP_TRANSITION, 4,
|
|
BD71828_INT_CHG_RANGED_TEMP_TRANSITION_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_CHG_STATE_TRANSITION, 4, BD71828_INT_CHG_STATE_TRANSITION_MASK),
|
|
/* Battery */
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_NORMAL, 5, BD71828_INT_BAT_TEMP_NORMAL_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_ERANGE, 5, BD71828_INT_BAT_TEMP_ERANGE_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_WARN, 5, BD71828_INT_BAT_TEMP_WARN_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_REMOVED, 5, BD71828_INT_BAT_REMOVED_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_DETECTED, 5, BD71828_INT_BAT_DETECTED_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_THERM_REMOVED, 5, BD71828_INT_THERM_REMOVED_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_THERM_DETECTED, 5, BD71828_INT_THERM_DETECTED_MASK),
|
|
/* Battery Mon 1 */
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_DEAD, 6, BD71828_INT_BAT_DEAD_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_RES, 6, BD71828_INT_BAT_SHORTC_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_DET, 6, BD71828_INT_BAT_SHORTC_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_RES, 6, BD71828_INT_BAT_LOW_VOLT_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_DET, 6, BD71828_INT_BAT_LOW_VOLT_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_RES, 6, BD71828_INT_BAT_OVER_VOLT_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_DET, 6, BD71828_INT_BAT_OVER_VOLT_DET_MASK),
|
|
/* Battery Mon 2 */
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_MON_RES, 7, BD71828_INT_BAT_MON_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_MON_DET, 7, BD71828_INT_BAT_MON_DET_MASK),
|
|
/* Battery Mon 3 (Coulomb counter) */
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON1, 8, BD71828_INT_BAT_CC_MON1_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON2, 8, BD71828_INT_BAT_CC_MON2_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON3, 8, BD71828_INT_BAT_CC_MON3_MASK),
|
|
/* Battery Mon 4 */
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_RES, 9, BD71828_INT_BAT_OVER_CURR_1_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_DET, 9, BD71828_INT_BAT_OVER_CURR_1_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_RES, 9, BD71828_INT_BAT_OVER_CURR_2_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_DET, 9, BD71828_INT_BAT_OVER_CURR_2_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_RES, 9, BD71828_INT_BAT_OVER_CURR_3_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_DET, 9, BD71828_INT_BAT_OVER_CURR_3_DET_MASK),
|
|
/* Temperature */
|
|
REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_RES, 10, BD71828_INT_TEMP_BAT_LOW_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_DET, 10, BD71828_INT_TEMP_BAT_LOW_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_RES, 10, BD71828_INT_TEMP_BAT_HI_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_DET, 10, BD71828_INT_TEMP_BAT_HI_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_RES, 10,
|
|
BD71828_INT_TEMP_CHIP_OVER_125_RES_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_DET, 10,
|
|
BD71828_INT_TEMP_CHIP_OVER_125_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_VF_DET, 10,
|
|
BD71828_INT_TEMP_CHIP_OVER_VF_DET_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_VF_RES, 10,
|
|
BD71828_INT_TEMP_CHIP_OVER_VF_RES_MASK),
|
|
/* RTC Alarm */
|
|
REGMAP_IRQ_REG(BD71828_INT_RTC0, 11, BD71828_INT_RTC0_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_RTC1, 11, BD71828_INT_RTC1_MASK),
|
|
REGMAP_IRQ_REG(BD71828_INT_RTC2, 11, BD71828_INT_RTC2_MASK),
|
|
};
|
|
|
|
static const struct regmap_irq bd72720_irqs[] = {
|
|
REGMAP_IRQ_REG(BD72720_INT_LONGPUSH, 0, BD72720_INT_LONGPUSH_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_MIDPUSH, 0, BD72720_INT_MIDPUSH_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_SHORTPUSH, 0, BD72720_INT_SHORTPUSH_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_PUSH, 0, BD72720_INT_PUSH_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_HALL_DET, 0, BD72720_INT_HALL_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_HALL_TGL, 0, BD72720_INT_HALL_TGL_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_WDOG, 0, BD72720_INT_WDOG_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_SWRESET, 0, BD72720_INT_SWRESET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_SEQ_DONE, 1, BD72720_INT_SEQ_DONE_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_PGFAULT, 1, BD72720_INT_PGFAULT_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_BUCK1_DVS, 2, BD72720_INT_BUCK1_DVS_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_BUCK2_DVS, 2, BD72720_INT_BUCK2_DVS_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_BUCK3_DVS, 2, BD72720_INT_BUCK3_DVS_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_BUCK4_DVS, 2, BD72720_INT_BUCK4_DVS_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_BUCK5_DVS, 2, BD72720_INT_BUCK5_DVS_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_BUCK6_DVS, 2, BD72720_INT_BUCK6_DVS_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_BUCK7_DVS, 2, BD72720_INT_BUCK7_DVS_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_BUCK8_DVS, 2, BD72720_INT_BUCK8_DVS_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_BUCK9_DVS, 3, BD72720_INT_BUCK9_DVS_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_BUCK10_DVS, 3, BD72720_INT_BUCK10_DVS_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_LDO1_DVS, 3, BD72720_INT_LDO1_DVS_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_LDO2_DVS, 3, BD72720_INT_LDO2_DVS_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_LDO3_DVS, 3, BD72720_INT_LDO3_DVS_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_LDO4_DVS, 3, BD72720_INT_LDO4_DVS_MASK),
|
|
|
|
REGMAP_IRQ_REG(BD72720_INT_VBUS_RMV, 4, BD72720_INT_VBUS_RMV_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_VBUS_DET, 4, BD72720_INT_VBUS_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_VBUS_MON_RES, 4, BD72720_INT_VBUS_MON_RES_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_VBUS_MON_DET, 4, BD72720_INT_VBUS_MON_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_VSYS_MON_RES, 5, BD72720_INT_VSYS_MON_RES_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_VSYS_MON_DET, 5, BD72720_INT_VSYS_MON_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_VSYS_UV_RES, 5, BD72720_INT_VSYS_UV_RES_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_VSYS_UV_DET, 5, BD72720_INT_VSYS_UV_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_VSYS_LO_RES, 5, BD72720_INT_VSYS_LO_RES_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_VSYS_LO_DET, 5, BD72720_INT_VSYS_LO_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_VSYS_OV_RES, 5, BD72720_INT_VSYS_OV_RES_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_VSYS_OV_DET, 5, BD72720_INT_VSYS_OV_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_BAT_ILIM, 6, BD72720_INT_BAT_ILIM_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_CHG_DONE, 6, BD72720_INT_CHG_DONE_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_EXTEMP_TOUT, 6, BD72720_INT_EXTEMP_TOUT_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_CHG_WDT_EXP, 6, BD72720_INT_CHG_WDT_EXP_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_BAT_MNT_OUT, 6, BD72720_INT_BAT_MNT_OUT_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_BAT_MNT_IN, 6, BD72720_INT_BAT_MNT_IN_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_CHG_TRNS, 6, BD72720_INT_CHG_TRNS_MASK),
|
|
|
|
REGMAP_IRQ_REG(BD72720_INT_VBAT_MON_RES, 7, BD72720_INT_VBAT_MON_RES_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_VBAT_MON_DET, 7, BD72720_INT_VBAT_MON_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_VBAT_SHT_RES, 7, BD72720_INT_VBAT_SHT_RES_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_VBAT_SHT_DET, 7, BD72720_INT_VBAT_SHT_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_VBAT_LO_RES, 7, BD72720_INT_VBAT_LO_RES_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_VBAT_LO_DET, 7, BD72720_INT_VBAT_LO_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_VBAT_OV_RES, 7, BD72720_INT_VBAT_OV_RES_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_VBAT_OV_DET, 7, BD72720_INT_VBAT_OV_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_BAT_RMV, 8, BD72720_INT_BAT_RMV_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_BAT_DET, 8, BD72720_INT_BAT_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_DBAT_DET, 8, BD72720_INT_DBAT_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_BAT_TEMP_TRNS, 8, BD72720_INT_BAT_TEMP_TRNS_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_LOBTMP_RES, 8, BD72720_INT_LOBTMP_RES_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_LOBTMP_DET, 8, BD72720_INT_LOBTMP_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_OVBTMP_RES, 8, BD72720_INT_OVBTMP_RES_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_OVBTMP_DET, 8, BD72720_INT_OVBTMP_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_OCUR1_RES, 9, BD72720_INT_OCUR1_RES_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_OCUR1_DET, 9, BD72720_INT_OCUR1_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_OCUR2_RES, 9, BD72720_INT_OCUR2_RES_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_OCUR2_DET, 9, BD72720_INT_OCUR2_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_OCUR3_RES, 9, BD72720_INT_OCUR3_RES_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_OCUR3_DET, 9, BD72720_INT_OCUR3_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_CC_MON1_DET, 10, BD72720_INT_CC_MON1_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_CC_MON2_DET, 10, BD72720_INT_CC_MON2_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_CC_MON3_DET, 10, BD72720_INT_CC_MON3_DET_MASK),
|
|
/*
|
|
* The GPIO1_IN and GPIO2_IN IRQs are generated from the PMIC's GPIO1 and GPIO2
|
|
* pins. Eg, they may be wired to other devices which can then use the PMIC as
|
|
* an interrupt controller. The GPIO1 and GPIO2 can have the IRQ type
|
|
* specified. All of the types (falling, rising, and both edges as well as low
|
|
* and high levels) are supported.
|
|
*/
|
|
BD72720_TYPED_IRQ_REG(BD72720_INT_GPIO1_IN, 10, BD72720_INT_GPIO1_IN_MASK, 0),
|
|
BD72720_TYPED_IRQ_REG(BD72720_INT_GPIO2_IN, 10, BD72720_INT_GPIO2_IN_MASK, 1),
|
|
REGMAP_IRQ_REG(BD72720_INT_VF125_RES, 11, BD72720_INT_VF125_RES_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_VF125_DET, 11, BD72720_INT_VF125_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_VF_RES, 11, BD72720_INT_VF_RES_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_VF_DET, 11, BD72720_INT_VF_DET_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_RTC0, 11, BD72720_INT_RTC0_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_RTC1, 11, BD72720_INT_RTC1_MASK),
|
|
REGMAP_IRQ_REG(BD72720_INT_RTC2, 11, BD72720_INT_RTC2_MASK),
|
|
};
|
|
|
|
static int bd72720_set_type_config(unsigned int **buf, unsigned int type,
|
|
const struct regmap_irq *irq_data,
|
|
int idx, void *irq_drv_data)
|
|
{
|
|
const struct regmap_irq_type *t = &irq_data->type;
|
|
|
|
/*
|
|
* The regmap IRQ ecpects IRQ_TYPE_EDGE_BOTH to be written to register
|
|
* as logical OR of the type_falling_val and type_rising_val. This is
|
|
* not how the BD72720 implements this configuration, hence we need
|
|
* to handle this specific case separately.
|
|
*/
|
|
if (type == IRQ_TYPE_EDGE_BOTH) {
|
|
buf[0][idx] &= ~t->type_reg_mask;
|
|
buf[0][idx] |= BD72720_GPIO_IRQ_TYPE_BOTH;
|
|
|
|
return 0;
|
|
}
|
|
|
|
return regmap_irq_set_type_config_simple(buf, type, irq_data, idx, irq_drv_data);
|
|
}
|
|
|
|
static const struct regmap_irq_chip bd71828_irq_chip = {
|
|
.name = "bd71828_irq",
|
|
.main_status = BD71828_REG_INT_MAIN,
|
|
.irqs = &bd71828_irqs[0],
|
|
.num_irqs = ARRAY_SIZE(bd71828_irqs),
|
|
.status_base = BD71828_REG_INT_BUCK,
|
|
.unmask_base = BD71828_REG_INT_MASK_BUCK,
|
|
.ack_base = BD71828_REG_INT_BUCK,
|
|
.init_ack_masked = true,
|
|
.num_regs = 12,
|
|
.num_main_regs = 1,
|
|
.sub_reg_offsets = &bd718xx_sub_irq_offsets[0],
|
|
.num_main_status_bits = 8,
|
|
.irq_reg_stride = 1,
|
|
};
|
|
|
|
static const struct regmap_irq_chip bd71815_irq_chip = {
|
|
.name = "bd71815_irq",
|
|
.main_status = BD71815_REG_INT_STAT,
|
|
.irqs = &bd71815_irqs[0],
|
|
.num_irqs = ARRAY_SIZE(bd71815_irqs),
|
|
.status_base = BD71815_REG_INT_STAT_01,
|
|
.unmask_base = BD71815_REG_INT_EN_01,
|
|
.ack_base = BD71815_REG_INT_STAT_01,
|
|
.init_ack_masked = true,
|
|
.num_regs = 12,
|
|
.num_main_regs = 1,
|
|
.sub_reg_offsets = &bd718xx_sub_irq_offsets[0],
|
|
.num_main_status_bits = 8,
|
|
.irq_reg_stride = 1,
|
|
};
|
|
|
|
static const unsigned int bd72720_irq_type_base[] = { BD72720_REG_GPIO1_CTRL };
|
|
|
|
static const struct regmap_irq_chip bd72720_irq_chip = {
|
|
.name = "bd72720_irq",
|
|
.main_status = BD72720_REG_INT_LVL1_STAT,
|
|
.irqs = &bd72720_irqs[0],
|
|
.num_irqs = ARRAY_SIZE(bd72720_irqs),
|
|
.status_base = BD72720_REG_INT_PS1_STAT,
|
|
.unmask_base = BD72720_REG_INT_PS1_EN,
|
|
.config_base = &bd72720_irq_type_base[0],
|
|
.num_config_bases = 1,
|
|
.num_config_regs = 2,
|
|
.set_type_config = bd72720_set_type_config,
|
|
.ack_base = BD72720_REG_INT_PS1_STAT,
|
|
.init_ack_masked = true,
|
|
.num_regs = 12,
|
|
.num_main_regs = 1,
|
|
.sub_reg_offsets = &bd72720_sub_irq_offsets[0],
|
|
.num_main_status_bits = 8,
|
|
.irq_reg_stride = 1,
|
|
};
|
|
|
|
static int set_clk_mode(struct device *dev, struct regmap *regmap,
|
|
int clkmode_reg)
|
|
{
|
|
int ret;
|
|
unsigned int open_drain;
|
|
|
|
ret = of_property_read_u32(dev->of_node, "rohm,clkout-open-drain", &open_drain);
|
|
if (ret) {
|
|
if (ret == -EINVAL)
|
|
return 0;
|
|
return ret;
|
|
}
|
|
if (open_drain > 1) {
|
|
dev_err(dev, "bad clk32kout mode configuration");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (open_drain)
|
|
return regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE,
|
|
OUT32K_MODE_OPEN_DRAIN);
|
|
|
|
return regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE,
|
|
OUT32K_MODE_CMOS);
|
|
}
|
|
|
|
static struct i2c_client *bd71828_dev;
|
|
static void bd71828_power_off(void)
|
|
{
|
|
while (true) {
|
|
s32 val;
|
|
|
|
/* We are not allowed to sleep, so do not use regmap involving mutexes here. */
|
|
val = i2c_smbus_read_byte_data(bd71828_dev, BD71828_REG_PS_CTRL_1);
|
|
if (val >= 0)
|
|
i2c_smbus_write_byte_data(bd71828_dev,
|
|
BD71828_REG_PS_CTRL_1,
|
|
BD71828_MASK_STATE_HBNT | (u8)val);
|
|
mdelay(500);
|
|
}
|
|
}
|
|
|
|
static void bd71828_remove_poweroff(void *data)
|
|
{
|
|
pm_power_off = NULL;
|
|
}
|
|
|
|
static struct regmap *bd72720_do_regmaps(struct i2c_client *i2c)
|
|
{
|
|
struct bd72720_regmaps *maps;
|
|
struct i2c_client *secondary_i2c;
|
|
|
|
secondary_i2c = devm_i2c_new_dummy_device(&i2c->dev, i2c->adapter,
|
|
BD72720_SECONDARY_I2C_SLAVE);
|
|
if (IS_ERR(secondary_i2c)) {
|
|
dev_err_probe(&i2c->dev, PTR_ERR(secondary_i2c), "Failed to get secondary I2C\n");
|
|
|
|
return ERR_CAST(secondary_i2c);
|
|
}
|
|
|
|
maps = devm_kzalloc(&i2c->dev, sizeof(*maps), GFP_KERNEL);
|
|
if (!maps)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
maps->map1_4b = devm_regmap_init_i2c(i2c, &bd72720_regmap_4b);
|
|
if (IS_ERR(maps->map1_4b))
|
|
return maps->map1_4b;
|
|
|
|
maps->map2_4c = devm_regmap_init_i2c(secondary_i2c, &bd72720_regmap_4c);
|
|
if (IS_ERR(maps->map2_4c))
|
|
return maps->map2_4c;
|
|
|
|
return devm_regmap_init(&i2c->dev, NULL, maps, &bd72720_wrapper_map_config);
|
|
}
|
|
|
|
static int bd71828_i2c_probe(struct i2c_client *i2c)
|
|
{
|
|
struct regmap_irq_chip_data *irq_data;
|
|
int ret;
|
|
struct regmap *regmap = NULL;
|
|
const struct regmap_config *regmap_config;
|
|
const struct regmap_irq_chip *irqchip;
|
|
unsigned int chip_type;
|
|
const struct mfd_cell *mfd;
|
|
int cells;
|
|
int button_irq;
|
|
int clkmode_reg;
|
|
int main_lvl_mask_reg = 0, main_lvl_val = 0;
|
|
|
|
if (!i2c->irq) {
|
|
dev_err(&i2c->dev, "No IRQ configured\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
chip_type = (unsigned int)(uintptr_t)
|
|
of_device_get_match_data(&i2c->dev);
|
|
switch (chip_type) {
|
|
case ROHM_CHIP_TYPE_BD71828:
|
|
mfd = bd71828_mfd_cells;
|
|
cells = ARRAY_SIZE(bd71828_mfd_cells);
|
|
regmap_config = &bd71828_regmap;
|
|
irqchip = &bd71828_irq_chip;
|
|
clkmode_reg = BD71828_REG_OUT32K;
|
|
button_irq = BD71828_INT_SHORTPUSH;
|
|
break;
|
|
case ROHM_CHIP_TYPE_BD71815:
|
|
mfd = bd71815_mfd_cells;
|
|
cells = ARRAY_SIZE(bd71815_mfd_cells);
|
|
regmap_config = &bd71815_regmap;
|
|
irqchip = &bd71815_irq_chip;
|
|
clkmode_reg = BD71815_REG_OUT32K;
|
|
/*
|
|
* If BD71817 support is needed we should be able to handle it
|
|
* with proper DT configs + BD71815 drivers + power-button.
|
|
* BD71815 data-sheet does not list the power-button IRQ so we
|
|
* don't use it.
|
|
*/
|
|
button_irq = 0;
|
|
break;
|
|
case ROHM_CHIP_TYPE_BD72720:
|
|
{
|
|
mfd = bd72720_mfd_cells;
|
|
cells = ARRAY_SIZE(bd72720_mfd_cells);
|
|
|
|
regmap = bd72720_do_regmaps(i2c);
|
|
if (IS_ERR(regmap))
|
|
return dev_err_probe(&i2c->dev, PTR_ERR(regmap),
|
|
"Failed to initialize Regmap\n");
|
|
|
|
irqchip = &bd72720_irq_chip;
|
|
clkmode_reg = BD72720_REG_OUT32K;
|
|
button_irq = BD72720_INT_SHORTPUSH;
|
|
main_lvl_mask_reg = BD72720_REG_INT_LVL1_EN;
|
|
main_lvl_val = BD72720_MASK_LVL1_EN_ALL;
|
|
break;
|
|
}
|
|
default:
|
|
dev_err(&i2c->dev, "Unknown device type");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (!regmap) {
|
|
regmap = devm_regmap_init_i2c(i2c, regmap_config);
|
|
if (IS_ERR(regmap))
|
|
return dev_err_probe(&i2c->dev, PTR_ERR(regmap),
|
|
"Failed to initialize Regmap\n");
|
|
}
|
|
|
|
ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, i2c->irq,
|
|
IRQF_ONESHOT, 0, irqchip, &irq_data);
|
|
if (ret)
|
|
return dev_err_probe(&i2c->dev, ret,
|
|
"Failed to add IRQ chip\n");
|
|
|
|
dev_dbg(&i2c->dev, "Registered %d IRQs for chip\n",
|
|
irqchip->num_irqs);
|
|
|
|
/*
|
|
* On some ICs the main IRQ register has corresponding mask register.
|
|
* This is not handled by the regmap IRQ. Let's enable all the main
|
|
* level IRQs here. Further writes to the main level MASK is not
|
|
* needed because masking is handled by the per IRQ 2.nd level MASK
|
|
* registers. 2.nd level masks are handled by the regmap IRQ.
|
|
*/
|
|
if (main_lvl_mask_reg) {
|
|
ret = regmap_write(regmap, main_lvl_mask_reg, main_lvl_val);
|
|
if (ret) {
|
|
return dev_err_probe(&i2c->dev, ret,
|
|
"Failed to enable main level IRQs\n");
|
|
}
|
|
}
|
|
if (button_irq) {
|
|
ret = regmap_irq_get_virq(irq_data, button_irq);
|
|
if (ret < 0)
|
|
return dev_err_probe(&i2c->dev, ret,
|
|
"Failed to get the power-key IRQ\n");
|
|
|
|
button.irq = ret;
|
|
}
|
|
|
|
ret = set_clk_mode(&i2c->dev, regmap, clkmode_reg);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, mfd, cells,
|
|
NULL, 0, regmap_irq_get_domain(irq_data));
|
|
if (ret)
|
|
return dev_err_probe(&i2c->dev, ret, "Failed to create subdevices\n");
|
|
|
|
if (of_device_is_system_power_controller(i2c->dev.of_node) &&
|
|
chip_type == ROHM_CHIP_TYPE_BD71828) {
|
|
if (!pm_power_off) {
|
|
bd71828_dev = i2c;
|
|
pm_power_off = bd71828_power_off;
|
|
ret = devm_add_action_or_reset(&i2c->dev,
|
|
bd71828_remove_poweroff,
|
|
NULL);
|
|
} else {
|
|
dev_warn(&i2c->dev, "Poweroff callback already assigned\n");
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct of_device_id bd71828_of_match[] = {
|
|
{
|
|
.compatible = "rohm,bd71828",
|
|
.data = (void *)ROHM_CHIP_TYPE_BD71828,
|
|
}, {
|
|
.compatible = "rohm,bd71815",
|
|
.data = (void *)ROHM_CHIP_TYPE_BD71815,
|
|
}, {
|
|
.compatible = "rohm,bd72720",
|
|
.data = (void *)ROHM_CHIP_TYPE_BD72720,
|
|
},
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, bd71828_of_match);
|
|
|
|
static struct i2c_driver bd71828_drv = {
|
|
.driver = {
|
|
.name = "rohm-bd71828",
|
|
.of_match_table = bd71828_of_match,
|
|
},
|
|
.probe = bd71828_i2c_probe,
|
|
};
|
|
module_i2c_driver(bd71828_drv);
|
|
|
|
MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
|
|
MODULE_DESCRIPTION("ROHM BD71828 Power Management IC driver");
|
|
MODULE_LICENSE("GPL");
|