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990c149c61
Master drivers currently manage Runtime PM individually, but all require runtime resume for bus operations. This can be centralized in common code. Add optional Runtime PM support to ensure the parent device is runtime resumed before bus operations and auto-suspended afterward. Notably, do not call ->bus_cleanup() if runtime resume fails. Master drivers that opt-in to core runtime PM support must take that into account. Also provide an option to allow IBIs and hot-joins while runtime suspended. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260113072702.16268-20-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
75 lines
2 KiB
C
75 lines
2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 Cadence Design Systems Inc.
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*
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* Author: Boris Brezillon <boris.brezillon@bootlin.com>
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*/
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#ifndef I3C_INTERNALS_H
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#define I3C_INTERNALS_H
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#include <linux/i3c/master.h>
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#include <linux/io.h>
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int __must_check i3c_bus_rpm_get(struct i3c_bus *bus);
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void i3c_bus_rpm_put(struct i3c_bus *bus);
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bool i3c_bus_rpm_ibi_allowed(struct i3c_bus *bus);
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void i3c_bus_normaluse_lock(struct i3c_bus *bus);
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void i3c_bus_normaluse_unlock(struct i3c_bus *bus);
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int i3c_dev_setdasa_locked(struct i3c_dev_desc *dev);
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int i3c_dev_do_xfers_locked(struct i3c_dev_desc *dev,
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struct i3c_xfer *xfers,
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int nxfers, enum i3c_xfer_mode mode);
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int i3c_dev_disable_ibi_locked(struct i3c_dev_desc *dev);
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int i3c_dev_enable_ibi_locked(struct i3c_dev_desc *dev);
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int i3c_dev_request_ibi_locked(struct i3c_dev_desc *dev,
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const struct i3c_ibi_setup *req);
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void i3c_dev_free_ibi_locked(struct i3c_dev_desc *dev);
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/**
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* i3c_writel_fifo - Write data buffer to 32bit FIFO
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* @addr: FIFO Address to write to
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* @buf: Pointer to the data bytes to write
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* @nbytes: Number of bytes to write
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*/
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static inline void i3c_writel_fifo(void __iomem *addr, const void *buf,
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int nbytes)
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{
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writesl(addr, buf, nbytes / 4);
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if (nbytes & 3) {
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u32 tmp = 0;
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memcpy(&tmp, buf + (nbytes & ~3), nbytes & 3);
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/*
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* writesl() instead of writel() to keep FIFO
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* byteorder on big-endian targets
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*/
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writesl(addr, &tmp, 1);
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}
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}
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/**
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* i3c_readl_fifo - Read data buffer from 32bit FIFO
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* @addr: FIFO Address to read from
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* @buf: Pointer to the buffer to store read bytes
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* @nbytes: Number of bytes to read
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*/
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static inline void i3c_readl_fifo(const void __iomem *addr, void *buf,
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int nbytes)
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{
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readsl(addr, buf, nbytes / 4);
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if (nbytes & 3) {
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u32 tmp;
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/*
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* readsl() instead of readl() to keep FIFO
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* byteorder on big-endian targets
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*/
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readsl(addr, &tmp, 1);
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memcpy(buf + (nbytes & ~3), &tmp, nbytes & 3);
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}
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}
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#endif /* I3C_INTERNAL_H */
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