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ef1df6cf69
In preparation for CXL VH (Virtual Host) topology protocol error handling,
add RAS capability registered mapping for all ports in a CXL VH topology.
This includes the RAS capabilities of Switch Upstream Ports, Switch
Downstream Ports, Host Bridge Ports ("upstream"), and Root Ports
("downstream")
Update cxl_port_add_dport() to map the upstream RAS capability on first
'dport' attach.
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Co-developed-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Tested-by: Terry Bowman <terry.bowman@amd.com>
Link: https://patch.msgid.link/20260131000403.2135324-8-dan.j.williams@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
104 lines
2.3 KiB
C
104 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
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#ifndef __CXL_PCI_H__
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#define __CXL_PCI_H__
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#include <linux/pci.h>
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#include "cxl.h"
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#define CXL_MEMORY_PROGIF 0x10
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/*
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* NOTE: Currently all the functions which are enabled for CXL require their
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* vectors to be in the first 16. Use this as the default max.
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*/
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#define CXL_PCI_DEFAULT_MAX_VECTORS 16
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/* Register Block Identifier (RBI) */
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enum cxl_regloc_type {
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CXL_REGLOC_RBI_EMPTY = 0,
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CXL_REGLOC_RBI_COMPONENT,
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CXL_REGLOC_RBI_VIRT,
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CXL_REGLOC_RBI_MEMDEV,
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CXL_REGLOC_RBI_PMU,
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CXL_REGLOC_RBI_TYPES
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};
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/*
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* Table Access DOE, CDAT Read Entry Response
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*
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* Spec refs:
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*
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* CXL 3.1 8.1.11, Table 8-14: Read Entry Response
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* CDAT Specification 1.03: 2 CDAT Data Structures
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*/
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struct cdat_header {
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__le32 length;
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u8 revision;
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u8 checksum;
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u8 reserved[6];
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__le32 sequence;
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} __packed;
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struct cdat_entry_header {
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u8 type;
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u8 reserved;
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__le16 length;
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} __packed;
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/*
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* The DOE CDAT read response contains a CDAT read entry (either the
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* CDAT header or a structure).
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*/
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union cdat_data {
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struct cdat_header header;
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struct cdat_entry_header entry;
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} __packed;
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/* There is an additional CDAT response header of 4 bytes. */
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struct cdat_doe_rsp {
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__le32 doe_header;
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u8 data[];
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} __packed;
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/*
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* CXL v3.0 6.2.3 Table 6-4
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* The table indicates that if PCIe Flit Mode is set, then CXL is in 256B flits
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* mode, otherwise it's 68B flits mode.
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*/
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static inline bool cxl_pci_flit_256(struct pci_dev *pdev)
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{
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u16 lnksta2;
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pcie_capability_read_word(pdev, PCI_EXP_LNKSTA2, &lnksta2);
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return lnksta2 & PCI_EXP_LNKSTA2_FLIT;
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}
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struct cxl_dev_state;
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void read_cdat_data(struct cxl_port *port);
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#ifdef CONFIG_CXL_RAS
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void cxl_cor_error_detected(struct pci_dev *pdev);
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pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
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pci_channel_state_t state);
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void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport);
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void devm_cxl_port_ras_setup(struct cxl_port *port);
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#else
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static inline void cxl_cor_error_detected(struct pci_dev *pdev) { }
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static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
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pci_channel_state_t state)
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{
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return PCI_ERS_RESULT_NONE;
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}
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static inline void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport)
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{
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}
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static inline void devm_cxl_port_ras_setup(struct cxl_port *port)
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{
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}
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#endif
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#endif /* __CXL_PCI_H__ */
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