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Merge branch '20260103-ufs_symbol_clk-v2-1-51828cc76236@oss.qualcomm.com' into clk-for-6.20

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Merge the addition of missing UFS PHY clocks in Hamoa GCC binding
through topic branch, to allow it to be merged into DeviceTree branch as
well.
This commit is contained in:
Bjorn Andersson 2026-01-03 08:39:43 -06:00
commit fd5b470f87
2 changed files with 10 additions and 1 deletions
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8
Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
View file

@ -62,6 +62,9 @@ properties:
- description: USB4_1 PHY max PIPE clock source
- description: USB4_2 PHY PCIE PIPE clock source
- description: USB4_2 PHY max PIPE clock source
- description: UFS PHY RX Symbol 0 clock source
- description: UFS PHY RX Symbol 1 clock source
- description: UFS PHY TX Symbol 0 clock source
power-domains:
description:
@ -121,7 +124,10 @@ examples:
<&usb4_1_phy_pcie_pipe_clk>,
<&usb4_1_phy_max_pipe_clk>,
<&usb4_2_phy_pcie_pipe_clk>,
<&usb4_2_phy_max_pipe_clk>;
<&usb4_2_phy_max_pipe_clk>,
<&ufs_phy_rx_symbol_0>,
<&ufs_phy_rx_symbol_1>,
<&ufs_phy_tx_symbol_0>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;

3
include/dt-bindings/clock/qcom,x1e80100-gcc.h
View file

@ -387,6 +387,9 @@
#define GCC_USB4_2_PHY_RX0_CLK_SRC 377
#define GCC_USB4_2_PHY_RX1_CLK_SRC 378
#define GCC_USB4_2_PHY_SYS_CLK_SRC 379
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 380
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 381
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 382
/* GCC power domains */
#define GCC_PCIE_0_TUNNEL_GDSC 0