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drm/i915/display: include intel_display_reg_defs.h from display regs files

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Some display register files include i915_reg_defs.h, some don't include
anything. Prefer intel_display_reg_defs.h in display.

Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
Link: https://lore.kernel.org/r/06c24e1f6a7a2f6b4801b0a079eec3cc924402a7.1749469962.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula 2025-06-09 14:53:36 +03:00
parent 5f105b2e49
commit fd585ee82c
8 changed files with 9 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

2
drivers/gpu/drm/i915/display/intel_cmtg_regs.h
View file

@ -6,7 +6,7 @@
#ifndef __INTEL_CMTG_REGS_H__
#define __INTEL_CMTG_REGS_H__
#include "i915_reg_defs.h"
#include "intel_display_reg_defs.h"
#define CMTG_CLK_SEL _MMIO(0x46160)
#define CMTG_CLK_SEL_A_MASK REG_GENMASK(31, 29)

2
drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
View file

@ -6,7 +6,7 @@
#ifndef __INTEL_COMBO_PHY_REGS__
#define __INTEL_COMBO_PHY_REGS__
#include "i915_reg_defs.h"
#include "intel_display_reg_defs.h"
#define _ICL_COMBOPHY_A 0x162000
#define _ICL_COMBOPHY_B 0x6C000

2
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
View file

@ -6,8 +6,8 @@
#ifndef __INTEL_CX0_PHY_REGS_H__
#define __INTEL_CX0_PHY_REGS_H__
#include "i915_reg_defs.h"
#include "intel_display_limits.h"
#include "intel_display_reg_defs.h"
/* DDI Buffer Control */
#define _DDI_CLK_VALFREQ_A 0x64030

2
drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
View file

@ -8,6 +8,8 @@
#include <linux/types.h>
#include "intel_display_reg_defs.h"
struct intel_dkl_phy_reg {
u32 reg:24;
u32 bank_idx:4;

2
drivers/gpu/drm/i915/display/intel_dmc_regs.h
View file

@ -6,7 +6,7 @@
#ifndef __INTEL_DMC_REGS_H__
#define __INTEL_DMC_REGS_H__
#include "i915_reg_defs.h"
#include "intel_display_reg_defs.h"
enum dmc_event_id {
DMC_EVENT_TRUE = 0x0,

2
drivers/gpu/drm/i915/display/intel_gmbus_regs.h
View file

@ -6,7 +6,7 @@
#ifndef __INTEL_GMBUS_REGS_H__
#define __INTEL_GMBUS_REGS_H__
#include "i915_reg_defs.h"
#include "intel_display_reg_defs.h"
#define __GMBUS_MMIO_BASE(__display) ((__display)->gmbus.mmio_base)

2
drivers/gpu/drm/i915/display/intel_hti_regs.h
View file

@ -6,7 +6,7 @@
#ifndef __INTEL_HTI_REGS_H__
#define __INTEL_HTI_REGS_H__
#include "i915_reg_defs.h"
#include "intel_display_reg_defs.h"
#define HDPORT_STATE _MMIO(0x45050)
#define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12)

2
drivers/gpu/drm/i915/display/intel_sbi_regs.h
View file

@ -4,7 +4,7 @@
#ifndef __INTEL_SBI_REGS_H__
#define __INTEL_SBI_REGS_H__
#include "i915_reg_defs.h"
#include "intel_display_reg_defs.h"
/*
* Sideband Interface (SBI) is programmed indirectly, via SBI_ADDR, which