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drm/amdgpu: add sdma 7.0 support for copy dcc buffer
1. Add dcc buffer flag for copy buffer 2. Add sdma 7.0 support copy dcc buffer Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Frank Min <Frank.Min@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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7c85e97083
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faa64f633c
4 changed files with 27 additions and 4 deletions
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@ -295,8 +295,8 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
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struct amdgpu_res_cursor src_mm, dst_mm;
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struct dma_fence *fence = NULL;
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int r = 0;
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uint32_t copy_flags = 0;
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struct amdgpu_bo *abo_src, *abo_dst;
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if (!adev->mman.buffer_funcs_enabled) {
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DRM_ERROR("Trying to move memory with ring turned off.\n");
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@ -325,8 +325,14 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
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if (r)
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goto error;
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abo_src = ttm_to_amdgpu_bo(src->bo);
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abo_dst = ttm_to_amdgpu_bo(dst->bo);
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if (tmz)
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copy_flags |= AMDGPU_COPY_FLAGS_TMZ;
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if (abo_src->flags & AMDGPU_GEM_CREATE_GFX12_DCC)
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copy_flags |= AMDGPU_COPY_FLAGS_READ_DECOMPRESSED;
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if (abo_dst->flags & AMDGPU_GEM_CREATE_GFX12_DCC)
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copy_flags |= AMDGPU_COPY_FLAGS_WRITE_COMPRESSED;
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r = amdgpu_copy_buffer(ring, from, to, cur_size, resv,
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&next, false, true, copy_flags);
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@ -112,6 +112,8 @@ struct amdgpu_copy_mem {
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};
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#define AMDGPU_COPY_FLAGS_TMZ (1 << 0)
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#define AMDGPU_COPY_FLAGS_READ_DECOMPRESSED (1 << 1)
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#define AMDGPU_COPY_FLAGS_WRITE_COMPRESSED (1 << 2)
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int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size);
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void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev);
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@ -148,7 +150,6 @@ int amdgpu_ttm_init(struct amdgpu_device *adev);
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void amdgpu_ttm_fini(struct amdgpu_device *adev);
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void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
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bool enable);
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int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
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uint64_t dst_offset, uint32_t byte_count,
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struct dma_resv *resv,
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@ -91,6 +91,14 @@
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#define SDMA_GCR_GLM_WB (1 << 4)
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#define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2)
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#define SDMA_GCR_GLI_INV(x) (((x) & 0x3) << 0)
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#define SDMA_DCC_DATA_FORMAT(x) ((x) & 0x3f)
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#define SDMA_DCC_NUM_TYPE(x) (((x) & 0x7) << 9)
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#define SDMA_DCC_READ_CM(x) (((x) & 0x3) << 16)
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#define SDMA_DCC_WRITE_CM(x) (((x) & 0x3) << 18)
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#define SDMA_DCC_MAX_COM(x) (((x) & 0x3) << 24)
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#define SDMA_DCC_MAX_UCOM(x) (((x) & 0x1) << 26)
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/*
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** Definitions for SDMA_PKT_COPY_LINEAR packet
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*/
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@ -1568,13 +1568,22 @@ static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib *ib,
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{
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ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
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SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
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SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0);
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SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0) |
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SDMA_PKT_COPY_LINEAR_HEADER_CPV((copy_flags &
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(AMDGPU_COPY_FLAGS_READ_DECOMPRESSED | AMDGPU_COPY_FLAGS_WRITE_COMPRESSED)) ? 1 : 0);
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ib->ptr[ib->length_dw++] = byte_count - 1;
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ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
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ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
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ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
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ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
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ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
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if ((copy_flags & (AMDGPU_COPY_FLAGS_READ_DECOMPRESSED | AMDGPU_COPY_FLAGS_WRITE_COMPRESSED)))
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ib->ptr[ib->length_dw++] = SDMA_DCC_DATA_FORMAT(4) | SDMA_DCC_NUM_TYPE(4) |
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((copy_flags & AMDGPU_COPY_FLAGS_READ_DECOMPRESSED) ? SDMA_DCC_READ_CM(2) : 0) |
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((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(1) : 0) |
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SDMA_DCC_MAX_COM(1) | SDMA_DCC_MAX_UCOM(1);
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}
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/**
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@ -1603,7 +1612,6 @@ static const struct amdgpu_buffer_funcs sdma_v7_0_buffer_funcs = {
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.copy_max_bytes = 0x400000,
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.copy_num_dw = 7,
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.emit_copy_buffer = sdma_v7_0_emit_copy_buffer,
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.fill_max_bytes = 0x400000,
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.fill_num_dw = 5,
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.emit_fill_buffer = sdma_v7_0_emit_fill_buffer,
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