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ASoC: loongson: Use BIT() macro

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Where applicable, use BIT() macro instead of shift operation to improve
readability.

Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Link: https://patch.msgid.link/ccca555c96f18c0ecf5f1544c82945ba651d105f.1725844530.git.zhoubinbin@loongson.cn
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Binbin Zhou 2024-09-09 15:19:05 +08:00 • committed by Mark Brown
parent 241c044e74
commit f2bd6f5b37
No known key found for this signature in database
GPG key ID: 24D68B725D5487D0
2 changed files with 17 additions and 17 deletions
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10
sound/soc/loongson/loongson_dma.c
View file

@ -17,11 +17,11 @@
#include "loongson_i2s.h"
/* DMA dma_order Register */
#define DMA_ORDER_STOP (1 << 4) /* DMA stop */
#define DMA_ORDER_START (1 << 3) /* DMA start */
#define DMA_ORDER_ASK_VALID (1 << 2) /* DMA ask valid flag */
#define DMA_ORDER_AXI_UNCO (1 << 1) /* Uncache access */
#define DMA_ORDER_ADDR_64 (1 << 0) /* 64bits address support */
#define DMA_ORDER_STOP BIT(4) /* DMA stop */
#define DMA_ORDER_START BIT(3) /* DMA start */
#define DMA_ORDER_ASK_VALID BIT(2) /* DMA ask valid flag */
#define DMA_ORDER_AXI_UNCO BIT(1) /* Uncache access */
#define DMA_ORDER_ADDR_64 BIT(0) /* 64bits address support */
#define DMA_ORDER_ASK_MASK (~0x1fUL) /* Ask addr mask */
#define DMA_ORDER_CTRL_MASK (0x0fUL) /* Control mask */

24
sound/soc/loongson/loongson_i2s.h
View file

@ -27,18 +27,18 @@
#define LS_I2S_RX_ORDER 0x110 /* RX DMA Order */
/* Loongson I2S Control Register */
#define I2S_CTRL_MCLK_READY (1 << 16) /* MCLK ready */
#define I2S_CTRL_MASTER (1 << 15) /* Master mode */
#define I2S_CTRL_MSB (1 << 14) /* MSB bit order */
#define I2S_CTRL_RX_EN (1 << 13) /* RX enable */
#define I2S_CTRL_TX_EN (1 << 12) /* TX enable */
#define I2S_CTRL_RX_DMA_EN (1 << 11) /* DMA RX enable */
#define I2S_CTRL_CLK_READY (1 << 8) /* BCLK ready */
#define I2S_CTRL_TX_DMA_EN (1 << 7) /* DMA TX enable */
#define I2S_CTRL_RESET (1 << 4) /* Controller soft reset */
#define I2S_CTRL_MCLK_EN (1 << 3) /* Enable MCLK */
#define I2S_CTRL_RX_INT_EN (1 << 1) /* RX interrupt enable */
#define I2S_CTRL_TX_INT_EN (1 << 0) /* TX interrupt enable */
#define I2S_CTRL_MCLK_READY BIT(16) /* MCLK ready */
#define I2S_CTRL_MASTER BIT(15) /* Master mode */
#define I2S_CTRL_MSB BIT(14) /* MSB bit order */
#define I2S_CTRL_RX_EN BIT(13) /* RX enable */
#define I2S_CTRL_TX_EN BIT(12) /* TX enable */
#define I2S_CTRL_RX_DMA_EN BIT(11) /* DMA RX enable */
#define I2S_CTRL_CLK_READY BIT(8) /* BCLK ready */
#define I2S_CTRL_TX_DMA_EN BIT(7) /* DMA TX enable */
#define I2S_CTRL_RESET BIT(4) /* Controller soft reset */
#define I2S_CTRL_MCLK_EN BIT(3) /* Enable MCLK */
#define I2S_CTRL_RX_INT_EN BIT(1) /* RX interrupt enable */
#define I2S_CTRL_TX_INT_EN BIT(0) /* TX interrupt enable */
#define LS_I2S_DRVNAME "loongson-i2s"