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fbdev enhancements for 7.0-rc1:

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A series with code cleanups for the au1100fb fbdev driver [Uwe Kleine-König].
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCaZc9DwAKCRD3ErUQojoP
 X8QwAQD/q7hoC/F4cfzDXB3SSH3mar47UvlOnYJYHNawz1ZKYQEAyX9yXAmDRh6z
 4nMdlHoBX20hExAJjNRmOFTeDHIyHg8=
 =papo
 -----END PGP SIGNATURE-----

Merge tag 'fbdev-for-7.0-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/linux-fbdev

Pull more fbdev updates from Helge Deller:
 "Code cleanups for the au1100fb fbdev driver (Uwe Kleine-König)"

* tag 'fbdev-for-7.0-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/linux-fbdev:
  fbdev: au1100fb: Replace license boilerplate by SPDX header
  fbdev: au1100fb: Fold au1100fb.h into its only user
  fbdev: au1100fb: Replace custom printk wrappers by pr_*
  fbdev: au1100fb: Make driver compilable on non-mips platforms
  fbdev: au1100fb: Use proper conversion specifiers in printk formats
  fbdev: au1100fb: Mark several local functions as static
  fbdev: au1100fb: Don't store device specific data in global variables
This commit is contained in:
Linus Torvalds 2026-02-20 15:24:21 -08:00
commit eee3666c92
3 changed files with 406 additions and 463 deletions
Download patch file Download diff file Expand all files Collapse all files

3
drivers/video/fbdev/Kconfig
View file

@ -1345,7 +1345,8 @@ endchoice
config FB_AU1100
bool "Au1100 LCD Driver"
depends on (FB = y) && MIPS_ALCHEMY
depends on FB = y
depends on MIPS_ALCHEMY || COMPILE_TEST
select FB_IOMEM_HELPERS
help
This is the framebuffer driver for the AMD Au1100 SOC. It can drive

487
drivers/video/fbdev/au1100fb.c
View file

@ -1,3 +1,4 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* BRIEF MODULE DESCRIPTION
* Au1100 LCD Driver.
@ -20,28 +21,13 @@
* Based on:
* linux/drivers/video/skeletonfb.c -- Skeleton for a frame buffer device
* Created 28 Dec 1997 by Geert Uytterhoeven
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#define pr_fmt(fmt) "au1100fb:" fmt "\n"
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
@ -55,11 +41,349 @@
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <asm/mach-au1x00/au1000.h>
#if defined(__BIG_ENDIAN)
#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
#else
#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
#endif
#define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
#define DEBUG 0
/********************************************************************/
#include "au1100fb.h"
/* LCD controller restrictions */
#define AU1100_LCD_MAX_XRES 800
#define AU1100_LCD_MAX_YRES 600
#define AU1100_LCD_MAX_BPP 16
#define AU1100_LCD_MAX_CLK 48000000
#define AU1100_LCD_NBR_PALETTE_ENTRIES 256
/* Default number of visible screen buffer to allocate */
#define AU1100FB_NBR_VIDEO_BUFFERS 4
/********************************************************************/
struct au1100fb_panel
{
const char name[25]; /* Full name <vendor>_<model> */
u32 control_base; /* Mode-independent control values */
u32 clkcontrol_base; /* Panel pixclock preferences */
u32 horztiming;
u32 verttiming;
u32 xres; /* Maximum horizontal resolution */
u32 yres; /* Maximum vertical resolution */
u32 bpp; /* Maximum depth supported */
};
struct au1100fb_regs
{
u32 lcd_control;
u32 lcd_intstatus;
u32 lcd_intenable;
u32 lcd_horztiming;
u32 lcd_verttiming;
u32 lcd_clkcontrol;
u32 lcd_dmaaddr0;
u32 lcd_dmaaddr1;
u32 lcd_words;
u32 lcd_pwmdiv;
u32 lcd_pwmhi;
u32 reserved[(0x0400-0x002C)/4];
u32 lcd_palettebase[256];
};
struct au1100fb_device {
struct fb_info info; /* FB driver info record */
struct au1100fb_panel *panel; /* Panel connected to this device */
struct au1100fb_regs* regs; /* Registers memory map */
size_t regs_len;
unsigned int regs_phys;
#ifdef CONFIG_PM
/* stores the register values during suspend */
struct au1100fb_regs pm_regs;
#endif
unsigned char* fb_mem; /* FrameBuffer memory map */
size_t fb_len;
dma_addr_t fb_phys;
int panel_idx;
struct clk *lcdclk;
struct device *dev;
};
/********************************************************************/
#define LCD_CONTROL (AU1100_LCD_BASE + 0x0)
#define LCD_CONTROL_SBB_BIT 21
#define LCD_CONTROL_SBB_MASK (0x3 << LCD_CONTROL_SBB_BIT)
#define LCD_CONTROL_SBB_1 (0 << LCD_CONTROL_SBB_BIT)
#define LCD_CONTROL_SBB_2 (1 << LCD_CONTROL_SBB_BIT)
#define LCD_CONTROL_SBB_3 (2 << LCD_CONTROL_SBB_BIT)
#define LCD_CONTROL_SBB_4 (3 << LCD_CONTROL_SBB_BIT)
#define LCD_CONTROL_SBPPF_BIT 18
#define LCD_CONTROL_SBPPF_MASK (0x7 << LCD_CONTROL_SBPPF_BIT)
#define LCD_CONTROL_SBPPF_655 (0 << LCD_CONTROL_SBPPF_BIT)
#define LCD_CONTROL_SBPPF_565 (1 << LCD_CONTROL_SBPPF_BIT)
#define LCD_CONTROL_SBPPF_556 (2 << LCD_CONTROL_SBPPF_BIT)
#define LCD_CONTROL_SBPPF_1555 (3 << LCD_CONTROL_SBPPF_BIT)
#define LCD_CONTROL_SBPPF_5551 (4 << LCD_CONTROL_SBPPF_BIT)
#define LCD_CONTROL_WP (1<<17)
#define LCD_CONTROL_WD (1<<16)
#define LCD_CONTROL_C (1<<15)
#define LCD_CONTROL_SM_BIT 13
#define LCD_CONTROL_SM_MASK (0x3 << LCD_CONTROL_SM_BIT)
#define LCD_CONTROL_SM_0 (0 << LCD_CONTROL_SM_BIT)
#define LCD_CONTROL_SM_90 (1 << LCD_CONTROL_SM_BIT)
#define LCD_CONTROL_SM_180 (2 << LCD_CONTROL_SM_BIT)
#define LCD_CONTROL_SM_270 (3 << LCD_CONTROL_SM_BIT)
#define LCD_CONTROL_DB (1<<12)
#define LCD_CONTROL_CCO (1<<11)
#define LCD_CONTROL_DP (1<<10)
#define LCD_CONTROL_PO_BIT 8
#define LCD_CONTROL_PO_MASK (0x3 << LCD_CONTROL_PO_BIT)
#define LCD_CONTROL_PO_00 (0 << LCD_CONTROL_PO_BIT)
#define LCD_CONTROL_PO_01 (1 << LCD_CONTROL_PO_BIT)
#define LCD_CONTROL_PO_10 (2 << LCD_CONTROL_PO_BIT)
#define LCD_CONTROL_PO_11 (3 << LCD_CONTROL_PO_BIT)
#define LCD_CONTROL_MPI (1<<7)
#define LCD_CONTROL_PT (1<<6)
#define LCD_CONTROL_PC (1<<5)
#define LCD_CONTROL_BPP_BIT 1
#define LCD_CONTROL_BPP_MASK (0x7 << LCD_CONTROL_BPP_BIT)
#define LCD_CONTROL_BPP_1 (0 << LCD_CONTROL_BPP_BIT)
#define LCD_CONTROL_BPP_2 (1 << LCD_CONTROL_BPP_BIT)
#define LCD_CONTROL_BPP_4 (2 << LCD_CONTROL_BPP_BIT)
#define LCD_CONTROL_BPP_8 (3 << LCD_CONTROL_BPP_BIT)
#define LCD_CONTROL_BPP_12 (4 << LCD_CONTROL_BPP_BIT)
#define LCD_CONTROL_BPP_16 (5 << LCD_CONTROL_BPP_BIT)
#define LCD_CONTROL_GO (1<<0)
#define LCD_INTSTATUS (AU1100_LCD_BASE + 0x4)
#define LCD_INTENABLE (AU1100_LCD_BASE + 0x8)
#define LCD_INT_SD (1<<7)
#define LCD_INT_OF (1<<6)
#define LCD_INT_UF (1<<5)
#define LCD_INT_SA (1<<3)
#define LCD_INT_SS (1<<2)
#define LCD_INT_S1 (1<<1)
#define LCD_INT_S0 (1<<0)
#define LCD_HORZTIMING (AU1100_LCD_BASE + 0xC)
#define LCD_HORZTIMING_HN2_BIT 24
#define LCD_HORZTIMING_HN2_MASK (0xFF << LCD_HORZTIMING_HN2_BIT)
#define LCD_HORZTIMING_HN2_N(N) ((((N)-1) << LCD_HORZTIMING_HN2_BIT) & LCD_HORZTIMING_HN2_MASK)
#define LCD_HORZTIMING_HN1_BIT 16
#define LCD_HORZTIMING_HN1_MASK (0xFF << LCD_HORZTIMING_HN1_BIT)
#define LCD_HORZTIMING_HN1_N(N) ((((N)-1) << LCD_HORZTIMING_HN1_BIT) & LCD_HORZTIMING_HN1_MASK)
#define LCD_HORZTIMING_HPW_BIT 10
#define LCD_HORZTIMING_HPW_MASK (0x3F << LCD_HORZTIMING_HPW_BIT)
#define LCD_HORZTIMING_HPW_N(N) ((((N)-1) << LCD_HORZTIMING_HPW_BIT) & LCD_HORZTIMING_HPW_MASK)
#define LCD_HORZTIMING_PPL_BIT 0
#define LCD_HORZTIMING_PPL_MASK (0x3FF << LCD_HORZTIMING_PPL_BIT)
#define LCD_HORZTIMING_PPL_N(N) ((((N)-1) << LCD_HORZTIMING_PPL_BIT) & LCD_HORZTIMING_PPL_MASK)
#define LCD_VERTTIMING (AU1100_LCD_BASE + 0x10)
#define LCD_VERTTIMING_VN2_BIT 24
#define LCD_VERTTIMING_VN2_MASK (0xFF << LCD_VERTTIMING_VN2_BIT)
#define LCD_VERTTIMING_VN2_N(N) ((((N)-1) << LCD_VERTTIMING_VN2_BIT) & LCD_VERTTIMING_VN2_MASK)
#define LCD_VERTTIMING_VN1_BIT 16
#define LCD_VERTTIMING_VN1_MASK (0xFF << LCD_VERTTIMING_VN1_BIT)
#define LCD_VERTTIMING_VN1_N(N) ((((N)-1) << LCD_VERTTIMING_VN1_BIT) & LCD_VERTTIMING_VN1_MASK)
#define LCD_VERTTIMING_VPW_BIT 10
#define LCD_VERTTIMING_VPW_MASK (0x3F << LCD_VERTTIMING_VPW_BIT)
#define LCD_VERTTIMING_VPW_N(N) ((((N)-1) << LCD_VERTTIMING_VPW_BIT) & LCD_VERTTIMING_VPW_MASK)
#define LCD_VERTTIMING_LPP_BIT 0
#define LCD_VERTTIMING_LPP_MASK (0x3FF << LCD_VERTTIMING_LPP_BIT)
#define LCD_VERTTIMING_LPP_N(N) ((((N)-1) << LCD_VERTTIMING_LPP_BIT) & LCD_VERTTIMING_LPP_MASK)
#define LCD_CLKCONTROL (AU1100_LCD_BASE + 0x14)
#define LCD_CLKCONTROL_IB (1<<18)
#define LCD_CLKCONTROL_IC (1<<17)
#define LCD_CLKCONTROL_IH (1<<16)
#define LCD_CLKCONTROL_IV (1<<15)
#define LCD_CLKCONTROL_BF_BIT 10
#define LCD_CLKCONTROL_BF_MASK (0x1F << LCD_CLKCONTROL_BF_BIT)
#define LCD_CLKCONTROL_BF_N(N) ((((N)-1) << LCD_CLKCONTROL_BF_BIT) & LCD_CLKCONTROL_BF_MASK)
#define LCD_CLKCONTROL_PCD_BIT 0
#define LCD_CLKCONTROL_PCD_MASK (0x3FF << LCD_CLKCONTROL_PCD_BIT)
#define LCD_CLKCONTROL_PCD_N(N) (((N) << LCD_CLKCONTROL_PCD_BIT) & LCD_CLKCONTROL_PCD_MASK)
#define LCD_DMAADDR0 (AU1100_LCD_BASE + 0x18)
#define LCD_DMAADDR1 (AU1100_LCD_BASE + 0x1C)
#define LCD_DMA_SA_BIT 5
#define LCD_DMA_SA_MASK (0x7FFFFFF << LCD_DMA_SA_BIT)
#define LCD_DMA_SA_N(N) ((N) & LCD_DMA_SA_MASK)
#define LCD_WORDS (AU1100_LCD_BASE + 0x20)
#define LCD_WRD_WRDS_BIT 0
#define LCD_WRD_WRDS_MASK (0xFFFFFFFF << LCD_WRD_WRDS_BIT)
#define LCD_WRD_WRDS_N(N) ((((N)-1) << LCD_WRD_WRDS_BIT) & LCD_WRD_WRDS_MASK)
#define LCD_PWMDIV (AU1100_LCD_BASE + 0x24)
#define LCD_PWMDIV_EN (1<<12)
#define LCD_PWMDIV_PWMDIV_BIT 0
#define LCD_PWMDIV_PWMDIV_MASK (0xFFF << LCD_PWMDIV_PWMDIV_BIT)
#define LCD_PWMDIV_PWMDIV_N(N) ((((N)-1) << LCD_PWMDIV_PWMDIV_BIT) & LCD_PWMDIV_PWMDIV_MASK)
#define LCD_PWMHI (AU1100_LCD_BASE + 0x28)
#define LCD_PWMHI_PWMHI1_BIT 12
#define LCD_PWMHI_PWMHI1_MASK (0xFFF << LCD_PWMHI_PWMHI1_BIT)
#define LCD_PWMHI_PWMHI1_N(N) (((N) << LCD_PWMHI_PWMHI1_BIT) & LCD_PWMHI_PWMHI1_MASK)
#define LCD_PWMHI_PWMHI0_BIT 0
#define LCD_PWMHI_PWMHI0_MASK (0xFFF << LCD_PWMHI_PWMHI0_BIT)
#define LCD_PWMHI_PWMHI0_N(N) (((N) << LCD_PWMHI_PWMHI0_BIT) & LCD_PWMHI_PWMHI0_MASK)
#define LCD_PALLETTEBASE (AU1100_LCD_BASE + 0x400)
#define LCD_PALLETTE_MONO_MI_BIT 0
#define LCD_PALLETTE_MONO_MI_MASK (0xF << LCD_PALLETTE_MONO_MI_BIT)
#define LCD_PALLETTE_MONO_MI_N(N) (((N)<< LCD_PALLETTE_MONO_MI_BIT) & LCD_PALLETTE_MONO_MI_MASK)
#define LCD_PALLETTE_COLOR_RI_BIT 8
#define LCD_PALLETTE_COLOR_RI_MASK (0xF << LCD_PALLETTE_COLOR_RI_BIT)
#define LCD_PALLETTE_COLOR_RI_N(N) (((N)<< LCD_PALLETTE_COLOR_RI_BIT) & LCD_PALLETTE_COLOR_RI_MASK)
#define LCD_PALLETTE_COLOR_GI_BIT 4
#define LCD_PALLETTE_COLOR_GI_MASK (0xF << LCD_PALLETTE_COLOR_GI_BIT)
#define LCD_PALLETTE_COLOR_GI_N(N) (((N)<< LCD_PALLETTE_COLOR_GI_BIT) & LCD_PALLETTE_COLOR_GI_MASK)
#define LCD_PALLETTE_COLOR_BI_BIT 0
#define LCD_PALLETTE_COLOR_BI_MASK (0xF << LCD_PALLETTE_COLOR_BI_BIT)
#define LCD_PALLETTE_COLOR_BI_N(N) (((N)<< LCD_PALLETTE_COLOR_BI_BIT) & LCD_PALLETTE_COLOR_BI_MASK)
#define LCD_PALLETTE_TFT_DC_BIT 0
#define LCD_PALLETTE_TFT_DC_MASK (0xFFFF << LCD_PALLETTE_TFT_DC_BIT)
#define LCD_PALLETTE_TFT_DC_N(N) (((N)<< LCD_PALLETTE_TFT_DC_BIT) & LCD_PALLETTE_TFT_DC_MASK)
/********************************************************************/
/* List of panels known to work with the AU1100 LCD controller.
* To add a new panel, enter the same specifications as the
* Generic_TFT one, and MAKE SURE that it doesn't conflicts
* with the controller restrictions. Restrictions are:
*
* STN color panels: max_bpp <= 12
* STN mono panels: max_bpp <= 4
* TFT panels: max_bpp <= 16
* max_xres <= 800
* max_yres <= 600
*/
static struct au1100fb_panel known_lcd_panels[] =
{
/* 800x600x16bpp CRT */
[0] = {
.name = "CRT_800x600_16",
.xres = 800,
.yres = 600,
.bpp = 16,
.control_base = 0x0004886A |
LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_DEFAULT_SBPPF |
LCD_CONTROL_BPP_16 | LCD_CONTROL_SBB_4,
.clkcontrol_base = 0x00020000,
.horztiming = 0x005aff1f,
.verttiming = 0x16000e57,
},
/* just the standard LCD */
[1] = {
.name = "WWPC LCD",
.xres = 240,
.yres = 320,
.bpp = 16,
.control_base = 0x0006806A,
.horztiming = 0x0A1010EF,
.verttiming = 0x0301013F,
.clkcontrol_base = 0x00018001,
},
/* Sharp 320x240 TFT panel */
[2] = {
.name = "Sharp_LQ038Q5DR01",
.xres = 320,
.yres = 240,
.bpp = 16,
.control_base =
( LCD_CONTROL_SBPPF_565
| LCD_CONTROL_C
| LCD_CONTROL_SM_0
| LCD_CONTROL_DEFAULT_PO
| LCD_CONTROL_PT
| LCD_CONTROL_PC
| LCD_CONTROL_BPP_16 ),
.horztiming =
( LCD_HORZTIMING_HN2_N(8)
| LCD_HORZTIMING_HN1_N(60)
| LCD_HORZTIMING_HPW_N(12)
| LCD_HORZTIMING_PPL_N(320) ),
.verttiming =
( LCD_VERTTIMING_VN2_N(5)
| LCD_VERTTIMING_VN1_N(17)
| LCD_VERTTIMING_VPW_N(1)
| LCD_VERTTIMING_LPP_N(240) ),
.clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
},
/* Hitachi SP14Q005 and possibly others */
[3] = {
.name = "Hitachi_SP14Qxxx",
.xres = 320,
.yres = 240,
.bpp = 4,
.control_base =
( LCD_CONTROL_C
| LCD_CONTROL_BPP_4 ),
.horztiming =
( LCD_HORZTIMING_HN2_N(1)
| LCD_HORZTIMING_HN1_N(1)
| LCD_HORZTIMING_HPW_N(1)
| LCD_HORZTIMING_PPL_N(320) ),
.verttiming =
( LCD_VERTTIMING_VN2_N(1)
| LCD_VERTTIMING_VN1_N(1)
| LCD_VERTTIMING_VPW_N(1)
| LCD_VERTTIMING_LPP_N(240) ),
.clkcontrol_base = LCD_CLKCONTROL_PCD_N(4),
},
/* Generic 640x480 TFT panel */
[4] = {
.name = "TFT_640x480_16",
.xres = 640,
.yres = 480,
.bpp = 16,
.control_base = 0x004806a | LCD_CONTROL_DEFAULT_PO,
.horztiming = 0x3434d67f,
.verttiming = 0x0e0e39df,
.clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
},
/* Pb1100 LCDB 640x480 PrimeView TFT panel */
[5] = {
.name = "PrimeView_640x480_16",
.xres = 640,
.yres = 480,
.bpp = 16,
.control_base = 0x0004886a | LCD_CONTROL_DEFAULT_PO,
.horztiming = 0x0e4bfe7f,
.verttiming = 0x210805df,
.clkcontrol_base = 0x00038001,
},
};
/********************************************************************/
/* Inline helpers */
#define panel_is_dual(panel) (panel->control_base & LCD_CONTROL_DP)
#define panel_is_active(panel)(panel->control_base & LCD_CONTROL_PT)
#define panel_is_color(panel) (panel->control_base & LCD_CONTROL_PC)
#define panel_swap_rgb(panel) (panel->control_base & LCD_CONTROL_CCO)
#if defined(CONFIG_COMPILE_TEST) && !defined(CONFIG_MIPS)
/* This is only defined to be able to compile this driver on non-mips platforms */
#define KSEG1ADDR(x) (x)
#endif
#define DRIVER_NAME "au1100fb"
#define DRIVER_DESC "LCD controller driver for AU1100 processors"
@ -84,21 +408,6 @@ struct fb_bitfield rgb_bitfields[][4] =
{ { 8, 4, 0 }, { 4, 4, 0 }, { 0, 4, 0 }, { 0, 0, 0 } },
};
static struct fb_fix_screeninfo au1100fb_fix = {
.id = "AU1100 FB",
.xpanstep = 1,
.ypanstep = 1,
.type = FB_TYPE_PACKED_PIXELS,
.accel = FB_ACCEL_NONE,
};
static struct fb_var_screeninfo au1100fb_var = {
.activate = FB_ACTIVATE_NOW,
.height = -1,
.width = -1,
.vmode = FB_VMODE_NONINTERLACED,
};
/* fb_blank
* Blank the screen. Depending on the mode, the screen will be
* activated with the backlight color, or desactivated
@ -107,7 +416,7 @@ static int au1100fb_fb_blank(int blank_mode, struct fb_info *fbi)
{
struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
print_dbg("fb_blank %d %p", blank_mode, fbi);
pr_devel("fb_blank %d %p", blank_mode, fbi);
switch (blank_mode) {
@ -135,7 +444,7 @@ static int au1100fb_fb_blank(int blank_mode, struct fb_info *fbi)
* Set hardware with var settings. This will enable the controller with a specific
* mode, normally validated with the fb_check_var method
*/
int au1100fb_setmode(struct au1100fb_device *fbdev)
static int au1100fb_setmode(struct au1100fb_device *fbdev)
{
struct fb_info *info;
u32 words;
@ -234,7 +543,8 @@ int au1100fb_setmode(struct au1100fb_device *fbdev)
/* fb_setcolreg
* Set color in LCD palette.
*/
int au1100fb_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *fbi)
static int au1100fb_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
unsigned transp, struct fb_info *fbi)
{
struct au1100fb_device *fbdev;
u32 *palette;
@ -293,14 +603,14 @@ int au1100fb_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned
/* fb_pan_display
* Pan display in x and/or y as specified
*/
int au1100fb_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fbi)
static int au1100fb_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fbi)
{
struct au1100fb_device *fbdev;
int dy;
fbdev = to_au1100fb_device(fbi);
print_dbg("fb_pan_display %p %p", var, fbi);
pr_devel("fb_pan_display %p %p", var, fbi);
if (!var || !fbdev) {
return -EINVAL;
@ -311,13 +621,13 @@ int au1100fb_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fbi)
return -EINVAL;
}
print_dbg("fb_pan_display 2 %p %p", var, fbi);
pr_devel("fb_pan_display 2 %p %p", var, fbi);
dy = var->yoffset - fbi->var.yoffset;
if (dy) {
u32 dmaaddr;
print_dbg("Panning screen of %d lines", dy);
pr_devel("Panning screen of %d lines", dy);
dmaaddr = fbdev->regs->lcd_dmaaddr0;
dmaaddr += (fbi->fix.line_length * dy);
@ -331,7 +641,7 @@ int au1100fb_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fbi)
fbdev->regs->lcd_dmaaddr0 = LCD_DMA_SA_N(dmaaddr);
}
}
print_dbg("fb_pan_display 3 %p %p", var, fbi);
pr_devel("fb_pan_display 3 %p %p", var, fbi);
return 0;
}
@ -340,13 +650,16 @@ int au1100fb_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fbi)
* Map video memory in user space. We don't use the generic fb_mmap method mainly
* to allow the use of the TLB streaming flag (CCA=6)
*/
int au1100fb_fb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
static int au1100fb_fb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
{
struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot);
#ifndef CONFIG_S390
/* On s390 pgprot_val() is a function and thus not a lvalue */
pgprot_val(vma->vm_page_prot) |= (6 << 9); //CCA=6
#endif
return dma_mmap_coherent(fbdev->dev, vma, fbdev->fb_mem, fbdev->fb_phys,
fbdev->fb_len);
@ -371,7 +684,7 @@ static int au1100fb_setup(struct au1100fb_device *fbdev)
int num_panels = ARRAY_SIZE(known_lcd_panels);
if (num_panels <= 0) {
print_err("No LCD panels supported by driver!");
pr_err("No LCD panels supported by driver!");
return -ENODEV;
}
@ -394,16 +707,16 @@ static int au1100fb_setup(struct au1100fb_device *fbdev)
}
}
if (i >= num_panels) {
print_warn("Panel '%s' not supported!", this_opt);
pr_warn("Panel '%s' not supported!", this_opt);
return -ENODEV;
}
}
/* Unsupported option */
else
print_warn("Unsupported option \"%s\"", this_opt);
pr_warn("Unsupported option \"%s\"", this_opt);
}
print_info("Panel=%s", fbdev->panel->name);
pr_info("Panel=%s", fbdev->panel->name);
return 0;
}
@ -428,26 +741,33 @@ static int au1100fb_drv_probe(struct platform_device *dev)
/* Allocate region for our registers and map them */
regs_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
if (!regs_res) {
print_err("fail to retrieve registers resource");
pr_err("fail to retrieve registers resource");
return -EFAULT;
}
au1100fb_fix.mmio_start = regs_res->start;
au1100fb_fix.mmio_len = resource_size(regs_res);
fbdev->info.fix = (struct fb_fix_screeninfo) {
.mmio_start = regs_res->start,
.mmio_len = resource_size(regs_res),
.id = "AU1100 FB",
.xpanstep = 1,
.ypanstep = 1,
.type = FB_TYPE_PACKED_PIXELS,
.accel = FB_ACCEL_NONE,
};
if (!devm_request_mem_region(&dev->dev,
au1100fb_fix.mmio_start,
au1100fb_fix.mmio_len,
fbdev->info.fix.mmio_start,
fbdev->info.fix.mmio_len,
DRIVER_NAME)) {
print_err("fail to lock memory region at 0x%08lx",
au1100fb_fix.mmio_start);
pr_err("fail to lock memory region at 0x%08lx",
fbdev->info.fix.mmio_start);
return -EBUSY;
}
fbdev->regs = (struct au1100fb_regs*)KSEG1ADDR(au1100fb_fix.mmio_start);
fbdev->regs = (struct au1100fb_regs*)KSEG1ADDR(fbdev->info.fix.mmio_start);
print_dbg("Register memory map at %p", fbdev->regs);
print_dbg("phys=0x%08x, size=%d", fbdev->regs_phys, fbdev->regs_len);
pr_devel("Register memory map at %p", fbdev->regs);
pr_devel("phys=0x%08x, size=%zu", fbdev->regs_phys, fbdev->regs_len);
c = clk_get(NULL, "lcd_intclk");
if (!IS_ERR(c)) {
@ -464,27 +784,32 @@ static int au1100fb_drv_probe(struct platform_device *dev)
PAGE_ALIGN(fbdev->fb_len),
&fbdev->fb_phys, GFP_KERNEL);
if (!fbdev->fb_mem) {
print_err("fail to allocate framebuffer (size: %dK))",
pr_err("fail to allocate framebuffer (size: %zuK))",
fbdev->fb_len / 1024);
return -ENOMEM;
}
au1100fb_fix.smem_start = fbdev->fb_phys;
au1100fb_fix.smem_len = fbdev->fb_len;
fbdev->info.fix.smem_start = fbdev->fb_phys;
fbdev->info.fix.smem_len = fbdev->fb_len;
print_dbg("Framebuffer memory map at %p", fbdev->fb_mem);
print_dbg("phys=0x%08x, size=%dK", fbdev->fb_phys, fbdev->fb_len / 1024);
pr_devel("Framebuffer memory map at %p", fbdev->fb_mem);
pr_devel("phys=0x%pad, size=%zuK", &fbdev->fb_phys, fbdev->fb_len / 1024);
/* load the panel info into the var struct */
au1100fb_var.bits_per_pixel = fbdev->panel->bpp;
au1100fb_var.xres = fbdev->panel->xres;
au1100fb_var.xres_virtual = au1100fb_var.xres;
au1100fb_var.yres = fbdev->panel->yres;
au1100fb_var.yres_virtual = au1100fb_var.yres;
fbdev->info.var = (struct fb_var_screeninfo) {
.activate = FB_ACTIVATE_NOW,
.height = -1,
.width = -1,
.vmode = FB_VMODE_NONINTERLACED,
.bits_per_pixel = fbdev->panel->bpp,
.xres = fbdev->panel->xres,
.xres_virtual = fbdev->panel->xres,
.yres = fbdev->panel->yres,
.yres_virtual = fbdev->panel->yres,
};
fbdev->info.screen_base = fbdev->fb_mem;
fbdev->info.fbops = &au1100fb_ops;
fbdev->info.fix = au1100fb_fix;
fbdev->info.pseudo_palette =
devm_kcalloc(&dev->dev, 16, sizeof(u32), GFP_KERNEL);
@ -492,19 +817,17 @@ static int au1100fb_drv_probe(struct platform_device *dev)
return -ENOMEM;
if (fb_alloc_cmap(&fbdev->info.cmap, AU1100_LCD_NBR_PALETTE_ENTRIES, 0) < 0) {
print_err("Fail to allocate colormap (%d entries)",
pr_err("Fail to allocate colormap (%d entries)",
AU1100_LCD_NBR_PALETTE_ENTRIES);
return -EFAULT;
}
fbdev->info.var = au1100fb_var;
/* Set h/w registers */
au1100fb_setmode(fbdev);
/* Register new framebuffer */
if (register_framebuffer(&fbdev->info) < 0) {
print_err("cannot register new framebuffer");
pr_err("cannot register new framebuffer");
goto failed;
}
@ -522,7 +845,7 @@ failed:
return -ENODEV;
}
void au1100fb_drv_remove(struct platform_device *dev)
static void au1100fb_drv_remove(struct platform_device *dev)
{
struct au1100fb_device *fbdev = NULL;
@ -545,9 +868,7 @@ void au1100fb_drv_remove(struct platform_device *dev)
}
#ifdef CONFIG_PM
static struct au1100fb_regs fbregs;
int au1100fb_drv_suspend(struct platform_device *dev, pm_message_t state)
static int au1100fb_drv_suspend(struct platform_device *dev, pm_message_t state)
{
struct au1100fb_device *fbdev = platform_get_drvdata(dev);
@ -559,12 +880,12 @@ int au1100fb_drv_suspend(struct platform_device *dev, pm_message_t state)
clk_disable(fbdev->lcdclk);
memcpy(&fbregs, fbdev->regs, sizeof(struct au1100fb_regs));
memcpy(&fbdev->pm_regs, fbdev->regs, sizeof(struct au1100fb_regs));
return 0;
}
int au1100fb_drv_resume(struct platform_device *dev)
static int au1100fb_drv_resume(struct platform_device *dev)
{
struct au1100fb_device *fbdev = platform_get_drvdata(dev);
int ret;
@ -572,7 +893,7 @@ int au1100fb_drv_resume(struct platform_device *dev)
if (!fbdev)
return 0;
memcpy(fbdev->regs, &fbregs, sizeof(struct au1100fb_regs));
memcpy(fbdev->regs, &fbdev->pm_regs, sizeof(struct au1100fb_regs));
ret = clk_enable(fbdev->lcdclk);
if (ret)

379
drivers/video/fbdev/au1100fb.h
View file

@ -1,379 +0,0 @@
/*
* BRIEF MODULE DESCRIPTION
* Hardware definitions for the Au1100 LCD controller
*
* Copyright 2002 MontaVista Software
* Copyright 2002 Alchemy Semiconductor
* Author: Alchemy Semiconductor, MontaVista Software
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _AU1100LCD_H
#define _AU1100LCD_H
#include <asm/mach-au1x00/au1000.h>
#define print_err(f, arg...) printk(KERN_ERR DRIVER_NAME ": " f "\n", ## arg)
#define print_warn(f, arg...) printk(KERN_WARNING DRIVER_NAME ": " f "\n", ## arg)
#define print_info(f, arg...) printk(KERN_INFO DRIVER_NAME ": " f "\n", ## arg)
#if DEBUG
#define print_dbg(f, arg...) printk(__FILE__ ": " f "\n", ## arg)
#else
#define print_dbg(f, arg...) do {} while (0)
#endif
#if defined(__BIG_ENDIAN)
#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
#else
#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
#endif
#define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
/********************************************************************/
/* LCD controller restrictions */
#define AU1100_LCD_MAX_XRES 800
#define AU1100_LCD_MAX_YRES 600
#define AU1100_LCD_MAX_BPP 16
#define AU1100_LCD_MAX_CLK 48000000
#define AU1100_LCD_NBR_PALETTE_ENTRIES 256
/* Default number of visible screen buffer to allocate */
#define AU1100FB_NBR_VIDEO_BUFFERS 4
/********************************************************************/
struct au1100fb_panel
{
const char name[25]; /* Full name <vendor>_<model> */
u32 control_base; /* Mode-independent control values */
u32 clkcontrol_base; /* Panel pixclock preferences */
u32 horztiming;
u32 verttiming;
u32 xres; /* Maximum horizontal resolution */
u32 yres; /* Maximum vertical resolution */
u32 bpp; /* Maximum depth supported */
};
struct au1100fb_regs
{
u32 lcd_control;
u32 lcd_intstatus;
u32 lcd_intenable;
u32 lcd_horztiming;
u32 lcd_verttiming;
u32 lcd_clkcontrol;
u32 lcd_dmaaddr0;
u32 lcd_dmaaddr1;
u32 lcd_words;
u32 lcd_pwmdiv;
u32 lcd_pwmhi;
u32 reserved[(0x0400-0x002C)/4];
u32 lcd_palettebase[256];
};
struct au1100fb_device {
struct fb_info info; /* FB driver info record */
struct au1100fb_panel *panel; /* Panel connected to this device */
struct au1100fb_regs* regs; /* Registers memory map */
size_t regs_len;
unsigned int regs_phys;
unsigned char* fb_mem; /* FrameBuffer memory map */
size_t fb_len;
dma_addr_t fb_phys;
int panel_idx;
struct clk *lcdclk;
struct device *dev;
};
/********************************************************************/
#define LCD_CONTROL (AU1100_LCD_BASE + 0x0)
#define LCD_CONTROL_SBB_BIT 21
#define LCD_CONTROL_SBB_MASK (0x3 << LCD_CONTROL_SBB_BIT)
#define LCD_CONTROL_SBB_1 (0 << LCD_CONTROL_SBB_BIT)
#define LCD_CONTROL_SBB_2 (1 << LCD_CONTROL_SBB_BIT)
#define LCD_CONTROL_SBB_3 (2 << LCD_CONTROL_SBB_BIT)
#define LCD_CONTROL_SBB_4 (3 << LCD_CONTROL_SBB_BIT)
#define LCD_CONTROL_SBPPF_BIT 18
#define LCD_CONTROL_SBPPF_MASK (0x7 << LCD_CONTROL_SBPPF_BIT)
#define LCD_CONTROL_SBPPF_655 (0 << LCD_CONTROL_SBPPF_BIT)
#define LCD_CONTROL_SBPPF_565 (1 << LCD_CONTROL_SBPPF_BIT)
#define LCD_CONTROL_SBPPF_556 (2 << LCD_CONTROL_SBPPF_BIT)
#define LCD_CONTROL_SBPPF_1555 (3 << LCD_CONTROL_SBPPF_BIT)
#define LCD_CONTROL_SBPPF_5551 (4 << LCD_CONTROL_SBPPF_BIT)
#define LCD_CONTROL_WP (1<<17)
#define LCD_CONTROL_WD (1<<16)
#define LCD_CONTROL_C (1<<15)
#define LCD_CONTROL_SM_BIT 13
#define LCD_CONTROL_SM_MASK (0x3 << LCD_CONTROL_SM_BIT)
#define LCD_CONTROL_SM_0 (0 << LCD_CONTROL_SM_BIT)
#define LCD_CONTROL_SM_90 (1 << LCD_CONTROL_SM_BIT)
#define LCD_CONTROL_SM_180 (2 << LCD_CONTROL_SM_BIT)
#define LCD_CONTROL_SM_270 (3 << LCD_CONTROL_SM_BIT)
#define LCD_CONTROL_DB (1<<12)
#define LCD_CONTROL_CCO (1<<11)
#define LCD_CONTROL_DP (1<<10)
#define LCD_CONTROL_PO_BIT 8
#define LCD_CONTROL_PO_MASK (0x3 << LCD_CONTROL_PO_BIT)
#define LCD_CONTROL_PO_00 (0 << LCD_CONTROL_PO_BIT)
#define LCD_CONTROL_PO_01 (1 << LCD_CONTROL_PO_BIT)
#define LCD_CONTROL_PO_10 (2 << LCD_CONTROL_PO_BIT)
#define LCD_CONTROL_PO_11 (3 << LCD_CONTROL_PO_BIT)
#define LCD_CONTROL_MPI (1<<7)
#define LCD_CONTROL_PT (1<<6)
#define LCD_CONTROL_PC (1<<5)
#define LCD_CONTROL_BPP_BIT 1
#define LCD_CONTROL_BPP_MASK (0x7 << LCD_CONTROL_BPP_BIT)
#define LCD_CONTROL_BPP_1 (0 << LCD_CONTROL_BPP_BIT)
#define LCD_CONTROL_BPP_2 (1 << LCD_CONTROL_BPP_BIT)
#define LCD_CONTROL_BPP_4 (2 << LCD_CONTROL_BPP_BIT)
#define LCD_CONTROL_BPP_8 (3 << LCD_CONTROL_BPP_BIT)
#define LCD_CONTROL_BPP_12 (4 << LCD_CONTROL_BPP_BIT)
#define LCD_CONTROL_BPP_16 (5 << LCD_CONTROL_BPP_BIT)
#define LCD_CONTROL_GO (1<<0)
#define LCD_INTSTATUS (AU1100_LCD_BASE + 0x4)
#define LCD_INTENABLE (AU1100_LCD_BASE + 0x8)
#define LCD_INT_SD (1<<7)
#define LCD_INT_OF (1<<6)
#define LCD_INT_UF (1<<5)
#define LCD_INT_SA (1<<3)
#define LCD_INT_SS (1<<2)
#define LCD_INT_S1 (1<<1)
#define LCD_INT_S0 (1<<0)
#define LCD_HORZTIMING (AU1100_LCD_BASE + 0xC)
#define LCD_HORZTIMING_HN2_BIT 24
#define LCD_HORZTIMING_HN2_MASK (0xFF << LCD_HORZTIMING_HN2_BIT)
#define LCD_HORZTIMING_HN2_N(N) ((((N)-1) << LCD_HORZTIMING_HN2_BIT) & LCD_HORZTIMING_HN2_MASK)
#define LCD_HORZTIMING_HN1_BIT 16
#define LCD_HORZTIMING_HN1_MASK (0xFF << LCD_HORZTIMING_HN1_BIT)
#define LCD_HORZTIMING_HN1_N(N) ((((N)-1) << LCD_HORZTIMING_HN1_BIT) & LCD_HORZTIMING_HN1_MASK)
#define LCD_HORZTIMING_HPW_BIT 10
#define LCD_HORZTIMING_HPW_MASK (0x3F << LCD_HORZTIMING_HPW_BIT)
#define LCD_HORZTIMING_HPW_N(N) ((((N)-1) << LCD_HORZTIMING_HPW_BIT) & LCD_HORZTIMING_HPW_MASK)
#define LCD_HORZTIMING_PPL_BIT 0
#define LCD_HORZTIMING_PPL_MASK (0x3FF << LCD_HORZTIMING_PPL_BIT)
#define LCD_HORZTIMING_PPL_N(N) ((((N)-1) << LCD_HORZTIMING_PPL_BIT) & LCD_HORZTIMING_PPL_MASK)
#define LCD_VERTTIMING (AU1100_LCD_BASE + 0x10)
#define LCD_VERTTIMING_VN2_BIT 24
#define LCD_VERTTIMING_VN2_MASK (0xFF << LCD_VERTTIMING_VN2_BIT)
#define LCD_VERTTIMING_VN2_N(N) ((((N)-1) << LCD_VERTTIMING_VN2_BIT) & LCD_VERTTIMING_VN2_MASK)
#define LCD_VERTTIMING_VN1_BIT 16
#define LCD_VERTTIMING_VN1_MASK (0xFF << LCD_VERTTIMING_VN1_BIT)
#define LCD_VERTTIMING_VN1_N(N) ((((N)-1) << LCD_VERTTIMING_VN1_BIT) & LCD_VERTTIMING_VN1_MASK)
#define LCD_VERTTIMING_VPW_BIT 10
#define LCD_VERTTIMING_VPW_MASK (0x3F << LCD_VERTTIMING_VPW_BIT)
#define LCD_VERTTIMING_VPW_N(N) ((((N)-1) << LCD_VERTTIMING_VPW_BIT) & LCD_VERTTIMING_VPW_MASK)
#define LCD_VERTTIMING_LPP_BIT 0
#define LCD_VERTTIMING_LPP_MASK (0x3FF << LCD_VERTTIMING_LPP_BIT)
#define LCD_VERTTIMING_LPP_N(N) ((((N)-1) << LCD_VERTTIMING_LPP_BIT) & LCD_VERTTIMING_LPP_MASK)
#define LCD_CLKCONTROL (AU1100_LCD_BASE + 0x14)
#define LCD_CLKCONTROL_IB (1<<18)
#define LCD_CLKCONTROL_IC (1<<17)
#define LCD_CLKCONTROL_IH (1<<16)
#define LCD_CLKCONTROL_IV (1<<15)
#define LCD_CLKCONTROL_BF_BIT 10
#define LCD_CLKCONTROL_BF_MASK (0x1F << LCD_CLKCONTROL_BF_BIT)
#define LCD_CLKCONTROL_BF_N(N) ((((N)-1) << LCD_CLKCONTROL_BF_BIT) & LCD_CLKCONTROL_BF_MASK)
#define LCD_CLKCONTROL_PCD_BIT 0
#define LCD_CLKCONTROL_PCD_MASK (0x3FF << LCD_CLKCONTROL_PCD_BIT)
#define LCD_CLKCONTROL_PCD_N(N) (((N) << LCD_CLKCONTROL_PCD_BIT) & LCD_CLKCONTROL_PCD_MASK)
#define LCD_DMAADDR0 (AU1100_LCD_BASE + 0x18)
#define LCD_DMAADDR1 (AU1100_LCD_BASE + 0x1C)
#define LCD_DMA_SA_BIT 5
#define LCD_DMA_SA_MASK (0x7FFFFFF << LCD_DMA_SA_BIT)
#define LCD_DMA_SA_N(N) ((N) & LCD_DMA_SA_MASK)
#define LCD_WORDS (AU1100_LCD_BASE + 0x20)
#define LCD_WRD_WRDS_BIT 0
#define LCD_WRD_WRDS_MASK (0xFFFFFFFF << LCD_WRD_WRDS_BIT)
#define LCD_WRD_WRDS_N(N) ((((N)-1) << LCD_WRD_WRDS_BIT) & LCD_WRD_WRDS_MASK)
#define LCD_PWMDIV (AU1100_LCD_BASE + 0x24)
#define LCD_PWMDIV_EN (1<<12)
#define LCD_PWMDIV_PWMDIV_BIT 0
#define LCD_PWMDIV_PWMDIV_MASK (0xFFF << LCD_PWMDIV_PWMDIV_BIT)
#define LCD_PWMDIV_PWMDIV_N(N) ((((N)-1) << LCD_PWMDIV_PWMDIV_BIT) & LCD_PWMDIV_PWMDIV_MASK)
#define LCD_PWMHI (AU1100_LCD_BASE + 0x28)
#define LCD_PWMHI_PWMHI1_BIT 12
#define LCD_PWMHI_PWMHI1_MASK (0xFFF << LCD_PWMHI_PWMHI1_BIT)
#define LCD_PWMHI_PWMHI1_N(N) (((N) << LCD_PWMHI_PWMHI1_BIT) & LCD_PWMHI_PWMHI1_MASK)
#define LCD_PWMHI_PWMHI0_BIT 0
#define LCD_PWMHI_PWMHI0_MASK (0xFFF << LCD_PWMHI_PWMHI0_BIT)
#define LCD_PWMHI_PWMHI0_N(N) (((N) << LCD_PWMHI_PWMHI0_BIT) & LCD_PWMHI_PWMHI0_MASK)
#define LCD_PALLETTEBASE (AU1100_LCD_BASE + 0x400)
#define LCD_PALLETTE_MONO_MI_BIT 0
#define LCD_PALLETTE_MONO_MI_MASK (0xF << LCD_PALLETTE_MONO_MI_BIT)
#define LCD_PALLETTE_MONO_MI_N(N) (((N)<< LCD_PALLETTE_MONO_MI_BIT) & LCD_PALLETTE_MONO_MI_MASK)
#define LCD_PALLETTE_COLOR_RI_BIT 8
#define LCD_PALLETTE_COLOR_RI_MASK (0xF << LCD_PALLETTE_COLOR_RI_BIT)
#define LCD_PALLETTE_COLOR_RI_N(N) (((N)<< LCD_PALLETTE_COLOR_RI_BIT) & LCD_PALLETTE_COLOR_RI_MASK)
#define LCD_PALLETTE_COLOR_GI_BIT 4
#define LCD_PALLETTE_COLOR_GI_MASK (0xF << LCD_PALLETTE_COLOR_GI_BIT)
#define LCD_PALLETTE_COLOR_GI_N(N) (((N)<< LCD_PALLETTE_COLOR_GI_BIT) & LCD_PALLETTE_COLOR_GI_MASK)
#define LCD_PALLETTE_COLOR_BI_BIT 0
#define LCD_PALLETTE_COLOR_BI_MASK (0xF << LCD_PALLETTE_COLOR_BI_BIT)
#define LCD_PALLETTE_COLOR_BI_N(N) (((N)<< LCD_PALLETTE_COLOR_BI_BIT) & LCD_PALLETTE_COLOR_BI_MASK)
#define LCD_PALLETTE_TFT_DC_BIT 0
#define LCD_PALLETTE_TFT_DC_MASK (0xFFFF << LCD_PALLETTE_TFT_DC_BIT)
#define LCD_PALLETTE_TFT_DC_N(N) (((N)<< LCD_PALLETTE_TFT_DC_BIT) & LCD_PALLETTE_TFT_DC_MASK)
/********************************************************************/
/* List of panels known to work with the AU1100 LCD controller.
* To add a new panel, enter the same specifications as the
* Generic_TFT one, and MAKE SURE that it doesn't conflicts
* with the controller restrictions. Restrictions are:
*
* STN color panels: max_bpp <= 12
* STN mono panels: max_bpp <= 4
* TFT panels: max_bpp <= 16
* max_xres <= 800
* max_yres <= 600
*/
static struct au1100fb_panel known_lcd_panels[] =
{
/* 800x600x16bpp CRT */
[0] = {
.name = "CRT_800x600_16",
.xres = 800,
.yres = 600,
.bpp = 16,
.control_base = 0x0004886A |
LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_DEFAULT_SBPPF |
LCD_CONTROL_BPP_16 | LCD_CONTROL_SBB_4,
.clkcontrol_base = 0x00020000,
.horztiming = 0x005aff1f,
.verttiming = 0x16000e57,
},
/* just the standard LCD */
[1] = {
.name = "WWPC LCD",
.xres = 240,
.yres = 320,
.bpp = 16,
.control_base = 0x0006806A,
.horztiming = 0x0A1010EF,
.verttiming = 0x0301013F,
.clkcontrol_base = 0x00018001,
},
/* Sharp 320x240 TFT panel */
[2] = {
.name = "Sharp_LQ038Q5DR01",
.xres = 320,
.yres = 240,
.bpp = 16,
.control_base =
( LCD_CONTROL_SBPPF_565
| LCD_CONTROL_C
| LCD_CONTROL_SM_0
| LCD_CONTROL_DEFAULT_PO
| LCD_CONTROL_PT
| LCD_CONTROL_PC
| LCD_CONTROL_BPP_16 ),
.horztiming =
( LCD_HORZTIMING_HN2_N(8)
| LCD_HORZTIMING_HN1_N(60)
| LCD_HORZTIMING_HPW_N(12)
| LCD_HORZTIMING_PPL_N(320) ),
.verttiming =
( LCD_VERTTIMING_VN2_N(5)
| LCD_VERTTIMING_VN1_N(17)
| LCD_VERTTIMING_VPW_N(1)
| LCD_VERTTIMING_LPP_N(240) ),
.clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
},
/* Hitachi SP14Q005 and possibly others */
[3] = {
.name = "Hitachi_SP14Qxxx",
.xres = 320,
.yres = 240,
.bpp = 4,
.control_base =
( LCD_CONTROL_C
| LCD_CONTROL_BPP_4 ),
.horztiming =
( LCD_HORZTIMING_HN2_N(1)
| LCD_HORZTIMING_HN1_N(1)
| LCD_HORZTIMING_HPW_N(1)
| LCD_HORZTIMING_PPL_N(320) ),
.verttiming =
( LCD_VERTTIMING_VN2_N(1)
| LCD_VERTTIMING_VN1_N(1)
| LCD_VERTTIMING_VPW_N(1)
| LCD_VERTTIMING_LPP_N(240) ),
.clkcontrol_base = LCD_CLKCONTROL_PCD_N(4),
},
/* Generic 640x480 TFT panel */
[4] = {
.name = "TFT_640x480_16",
.xres = 640,
.yres = 480,
.bpp = 16,
.control_base = 0x004806a | LCD_CONTROL_DEFAULT_PO,
.horztiming = 0x3434d67f,
.verttiming = 0x0e0e39df,
.clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
},
/* Pb1100 LCDB 640x480 PrimeView TFT panel */
[5] = {
.name = "PrimeView_640x480_16",
.xres = 640,
.yres = 480,
.bpp = 16,
.control_base = 0x0004886a | LCD_CONTROL_DEFAULT_PO,
.horztiming = 0x0e4bfe7f,
.verttiming = 0x210805df,
.clkcontrol_base = 0x00038001,
},
};
/********************************************************************/
/* Inline helpers */
#define panel_is_dual(panel) (panel->control_base & LCD_CONTROL_DP)
#define panel_is_active(panel)(panel->control_base & LCD_CONTROL_PT)
#define panel_is_color(panel) (panel->control_base & LCD_CONTROL_PC)
#define panel_swap_rgb(panel) (panel->control_base & LCD_CONTROL_CCO)
#endif /* _AU1100LCD_H */