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pinctrl: renesas: rzg2l: Add function pointer for PMC register write

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Introduces pmc_writeb() function pointer, in the struct
rzg2l_pinctrl_data to facilitate writing to the PMC register.  On the
RZ/V2H(P) SoC, unlocking the PWPR.REGWE_A bit before writing to PMC
registers is required, whereas this is not the case for the existing
RZ/G2L family.  This addition enables the reuse of existing code for
RZ/V2H(P).  Additionally, populate this function pointer with
appropriate data for existing SoCs.

Note that this functionality is only handled in rzg2l_gpio_request(), as
PMC unlock/lock during PFC setup will be taken care of in the
pwpr_pfc_lock_unlock() function pointer.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-9-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar 2024-05-30 18:38:50 +01:00 • committed by Geert Uytterhoeven
parent 14c32dc1f6
commit ede014cd1e
1 changed files with 10 additions and 1 deletions
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11
drivers/pinctrl/renesas/pinctrl-rzg2l.c
View file

@ -254,6 +254,7 @@ struct rzg2l_pinctrl_data {
const u64 *variable_pin_cfg;
unsigned int n_variable_pin_cfg;
void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);
void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);
};
/**
@ -383,6 +384,11 @@ static const u64 r9a07g043f_variable_pin_cfg[] = {
};
#endif
static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)
{
writeb(val, pctrl->base + offset);
}
static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
u8 pin, u8 off, u8 func)
{
@ -1329,7 +1335,7 @@ static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset)
/* Select GPIO mode in PMC Register */
reg8 = readb(pctrl->base + PMC(off));
reg8 &= ~BIT(bit);
writeb(reg8, pctrl->base + PMC(off));
pctrl->data->pmc_writeb(pctrl, reg8, PMC(off));
spin_unlock_irqrestore(&pctrl->lock, flags);
@ -2616,6 +2622,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
.n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg),
#endif
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzg2l_pmc_writeb,
};
static struct rzg2l_pinctrl_data r9a07g044_data = {
@ -2628,6 +2635,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
.hwcfg = &rzg2l_hwcfg,
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzg2l_pmc_writeb,
};
static struct rzg2l_pinctrl_data r9a08g045_data = {
@ -2639,6 +2647,7 @@ static struct rzg2l_pinctrl_data r9a08g045_data = {
.n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins),
.hwcfg = &rzg3s_hwcfg,
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzg2l_pmc_writeb,
};
static const struct of_device_id rzg2l_pinctrl_of_table[] = {