mirror of
https://github.com/torvalds/linux.git
synced 2026-03-08 04:44:45 +01:00
intel-pinctrl for v6.20-1
* Add Nova Lake to the list of supported platforms by platform driver * Update Kconfig help text to clarify which drivers supports which platforms * Convert more Intel pin control drivers to use intel_gpio_add_pin_ranges() -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAml3gcIACgkQb7wzTHR8 rCgXHBAAnAvr6TINDxHl8ofSTSCNOsVy6yzdtRrVl9D6j/o0BqL8sqEgV0zfhHrN EEzbUA67SmE5qASiqalpwxQYDJ9Ej5SVdBM+HtFU0k88COMDyMy7itZEM/urhndC xx9x4hzWcTbiXacEDMdL2xAccnz31bQbJZXw5NW31k/283VobAO4IcjYslHZTXZ+ Kg0H8JqRogT/CRbWFIKtJshBwevDJHcnbrobd9ZgliDYqg3crNntb0jJZi15GDS/ WCU8LSKqvdN7x5it/ugMfmmlUUgHPOTVzNHgdjH6WYGqfqbi43BF4qFDehKXW5Rc 04Z6Te8krXavajkWitc2B4NeSbvRoCQrDj0FDB10ejcNrWbEAxUEUMKptjfZwmJ1 ktubDjQW7VBuuO307f6X5s0DqSC0xse9qfFnxHPDwoHnWn0k2xadLCP4EjKMriGm humJqjMlEQNgMrFsTBUs/Q8CYJ513ZPty1w/lN/IvS+NlLTsBYbWjIbEF1wLCSdJ Q1hOwk6Egx31Z3tDWekCKW6fgpQ0GV5pqSsix5xsxX09+sKH9sHGK2mwfESXnrke V0zMi2kgMhlGeLfDrlGDh+kGWiXeFHaSOjoWqw7dwOCgiSiRHaJjQJFTU6OYbHo2 xWPJ3te85nfH9FmjXBImguVwyjX1gl+24DxAiV6L8J9mqZQ3HdM= =ReWs -----END PGP SIGNATURE----- Merge tag 'intel-pinctrl-v6.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v6.20-1 * Add Nova Lake to the list of supported platforms by platform driver * Update Kconfig help text to clarify which drivers supports which platforms * Convert more Intel pin control drivers to use intel_gpio_add_pin_ranges() Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Linus Walleij
commit
ebd2f48dff
3 changed files with 50 additions and 40 deletions
|
|
@ -45,6 +45,7 @@ config PINCTRL_INTEL_PLATFORM
|
|||
of Intel PCH pins and using them as GPIOs. Currently the following
|
||||
Intel SoCs / platforms require this to be functional:
|
||||
- Lunar Lake
|
||||
- Nova Lake
|
||||
- Panther Lake
|
||||
|
||||
config PINCTRL_ALDERLAKE
|
||||
|
|
@ -52,7 +53,10 @@ config PINCTRL_ALDERLAKE
|
|||
select PINCTRL_INTEL
|
||||
help
|
||||
This pinctrl driver provides an interface that allows configuring
|
||||
of Intel Alder Lake PCH pins and using them as GPIOs.
|
||||
PCH pins of the following platforms and using them as GPIOs:
|
||||
- Alder Lake HX, N, and S
|
||||
- Raptor Lake HX, E, and S
|
||||
- Twin Lake
|
||||
|
||||
config PINCTRL_BROXTON
|
||||
tristate "Intel Broxton pinctrl and GPIO driver"
|
||||
|
|
@ -136,15 +140,17 @@ config PINCTRL_METEORLAKE
|
|||
select PINCTRL_INTEL
|
||||
help
|
||||
This pinctrl driver provides an interface that allows configuring
|
||||
of Intel Meteor Lake pins and using them as GPIOs.
|
||||
SoC pins of the following platforms and using them as GPIOs:
|
||||
- Arrow Lake (all variants)
|
||||
- Meteor Lake (all variants)
|
||||
|
||||
config PINCTRL_METEORPOINT
|
||||
tristate "Intel Meteor Point pinctrl and GPIO driver"
|
||||
select PINCTRL_INTEL
|
||||
help
|
||||
Meteor Point is the PCH of Intel Meteor Lake. This pinctrl driver
|
||||
provides an interface that allows configuring of PCH pins and
|
||||
using them as GPIOs.
|
||||
This pinctrl driver provides an interface that allows configuring
|
||||
PCH pins of the following platforms and using them as GPIOs:
|
||||
- Arrow Lake HX and S
|
||||
|
||||
config PINCTRL_SUNRISEPOINT
|
||||
tristate "Intel Sunrisepoint pinctrl and GPIO driver"
|
||||
|
|
@ -159,7 +165,11 @@ config PINCTRL_TIGERLAKE
|
|||
select PINCTRL_INTEL
|
||||
help
|
||||
This pinctrl driver provides an interface that allows configuring
|
||||
of Intel Tiger Lake PCH pins and using them as GPIOs.
|
||||
PCH pins of the following platforms and using them as GPIOs:
|
||||
- Alder Lake H, P, PS, and U
|
||||
- Raptor Lake H, P, PS, PX, and U
|
||||
- Rocket Lake S
|
||||
- Tiger Lake (all variants)
|
||||
|
||||
source "drivers/pinctrl/intel/Kconfig.tng"
|
||||
endmenu
|
||||
|
|
|
|||
|
|
@ -101,10 +101,12 @@ struct intel_pad_context {
|
|||
u32 val;
|
||||
};
|
||||
|
||||
#define COMMUNITY(p, n, map) \
|
||||
#define BYT_COMMUNITY(p, n, g, map) \
|
||||
{ \
|
||||
.pin_base = (p), \
|
||||
.npins = (n), \
|
||||
.gpps = (g), \
|
||||
.ngpps = ARRAY_SIZE(g), \
|
||||
.pad_map = (map),\
|
||||
}
|
||||
|
||||
|
|
@ -360,8 +362,15 @@ static const struct intel_function byt_score_functions[] = {
|
|||
FUNCTION("gpio", byt_score_gpio_groups),
|
||||
};
|
||||
|
||||
static const struct intel_padgroup byt_score_gpps[] = {
|
||||
INTEL_GPP(0, 0, 31, 0),
|
||||
INTEL_GPP(1, 32, 63, 32),
|
||||
INTEL_GPP(2, 64, 95, 64),
|
||||
INTEL_GPP(3, 96, 101, 96),
|
||||
};
|
||||
|
||||
static const struct intel_community byt_score_communities[] = {
|
||||
COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
|
||||
BYT_COMMUNITY(0, 102, byt_score_gpps, byt_score_pins_map),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data byt_score_soc_data = {
|
||||
|
|
@ -483,8 +492,13 @@ static const struct intel_function byt_sus_functions[] = {
|
|||
FUNCTION("pmu_clk", byt_sus_pmu_clk_groups),
|
||||
};
|
||||
|
||||
static const struct intel_padgroup byt_sus_gpps[] = {
|
||||
INTEL_GPP(0, 0, 31, 0),
|
||||
INTEL_GPP(1, 32, 43, 32),
|
||||
};
|
||||
|
||||
static const struct intel_community byt_sus_communities[] = {
|
||||
COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
|
||||
BYT_COMMUNITY(0, 44, byt_sus_gpps, byt_sus_pins_map),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data byt_sus_soc_data = {
|
||||
|
|
@ -536,8 +550,12 @@ static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
|
|||
3, 6, 10, 13, 2, 5, 9, 7,
|
||||
};
|
||||
|
||||
static const struct intel_padgroup byt_ncore_gpps[] = {
|
||||
INTEL_GPP(0, 0, 27, 0),
|
||||
};
|
||||
|
||||
static const struct intel_community byt_ncore_communities[] = {
|
||||
COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
|
||||
BYT_COMMUNITY(0, 28, byt_ncore_gpps, byt_ncore_pins_map),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data byt_ncore_soc_data = {
|
||||
|
|
@ -1490,19 +1508,6 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)
|
||||
{
|
||||
struct intel_pinctrl *vg = gpiochip_get_data(chip);
|
||||
struct device *dev = vg->dev;
|
||||
int ret;
|
||||
|
||||
ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "failed to add GPIO pin range\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int byt_gpio_probe(struct intel_pinctrl *vg)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(vg->dev);
|
||||
|
|
@ -1515,7 +1520,7 @@ static int byt_gpio_probe(struct intel_pinctrl *vg)
|
|||
gc->label = dev_name(vg->dev);
|
||||
gc->base = -1;
|
||||
gc->can_sleep = false;
|
||||
gc->add_pin_ranges = byt_gpio_add_pin_ranges;
|
||||
gc->add_pin_ranges = intel_gpio_add_pin_ranges;
|
||||
gc->parent = vg->dev;
|
||||
gc->ngpio = vg->soc->npins;
|
||||
|
||||
|
|
|
|||
|
|
@ -29,10 +29,12 @@
|
|||
|
||||
#include "pinctrl-intel.h"
|
||||
|
||||
#define COMMUNITY(p, n) \
|
||||
#define LPTLP_COMMUNITY(p, n, g) \
|
||||
{ \
|
||||
.pin_base = (p), \
|
||||
.npins = (n), \
|
||||
.gpps = (g), \
|
||||
.ngpps = ARRAY_SIZE(g), \
|
||||
}
|
||||
|
||||
static const struct pinctrl_pin_desc lptlp_pins[] = {
|
||||
|
|
@ -133,8 +135,14 @@ static const struct pinctrl_pin_desc lptlp_pins[] = {
|
|||
PINCTRL_PIN(94, "GP94_UART0_CTSB"),
|
||||
};
|
||||
|
||||
static const struct intel_padgroup lptlp_gpps[] = {
|
||||
INTEL_GPP(0, 0, 31, 0),
|
||||
INTEL_GPP(1, 32, 63, 32),
|
||||
INTEL_GPP(2, 64, 94, 64),
|
||||
};
|
||||
|
||||
static const struct intel_community lptlp_communities[] = {
|
||||
COMMUNITY(0, 95),
|
||||
LPTLP_COMMUNITY(0, 95, lptlp_gpps),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data lptlp_soc_data = {
|
||||
|
|
@ -692,19 +700,6 @@ static int lp_gpio_irq_init_hw(struct gpio_chip *chip)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int lp_gpio_add_pin_ranges(struct gpio_chip *chip)
|
||||
{
|
||||
struct intel_pinctrl *lg = gpiochip_get_data(chip);
|
||||
struct device *dev = lg->dev;
|
||||
int ret;
|
||||
|
||||
ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "failed to add GPIO pin range\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lp_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct intel_pinctrl_soc_data *soc;
|
||||
|
|
@ -777,7 +772,7 @@ static int lp_gpio_probe(struct platform_device *pdev)
|
|||
gc->base = -1;
|
||||
gc->ngpio = LP_NUM_GPIO;
|
||||
gc->can_sleep = false;
|
||||
gc->add_pin_ranges = lp_gpio_add_pin_ranges;
|
||||
gc->add_pin_ranges = intel_gpio_add_pin_ranges;
|
||||
gc->parent = dev;
|
||||
|
||||
/* set up interrupts */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue