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ASoC: rockchip: spdif: Cleanups and port features
Merge series from Sebastian Reichel <sebastian.reichel@collabora.com>: I'm currently working on DisplayPort audio support for the Rockchip RK3588/RK3576 SoCs, which preferrably use S/PDIF as DAI source. Apparently the upstream Rockchip S/PDIF driver is lacking a couple of features right now, which are necessary to get things going (i.e. setting the sysclk from the machine driver). I found the missing bits in Rockchip's 6.1 BSP kernel and ported them over. This series effectly brings the mainline kernel on-par with the BSP driver, but also contains a couple of cleanup patches of my own to bring the driver to the modern age.
This commit is contained in:
Mark Brown
commit
dacaa439fa
3 changed files with 176 additions and 107 deletions
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@ -41,6 +41,7 @@ config SND_SOC_ROCKCHIP_SAI
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config SND_SOC_ROCKCHIP_SPDIF
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tristate "Rockchip SPDIF Device Driver"
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select SND_PCM_IEC958
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select SND_SOC_GENERIC_DMAENGINE_PCM
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help
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Say Y or M if you want to add support for SPDIF driver for
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@ -5,10 +5,11 @@
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*
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* Copyright (c) 2014 Rockchip Electronics Co. Ltd.
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* Author: Jianqun <jay.xu@rock-chips.com>
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* Copyright (c) 2015 Collabora Ltd.
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* Copyright (c) 2015-2026 Collabora Ltd.
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* Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
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*/
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#include <linux/bitfield.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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@ -16,6 +17,7 @@
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <sound/pcm_params.h>
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#include <sound/pcm_iec958.h>
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#include <sound/dmaengine_pcm.h>
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#include "rockchip_spdif.h"
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@ -27,7 +29,25 @@ enum rk_spdif_type {
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RK_SPDIF_RK3366,
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};
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#define RK3288_GRF_SOC_CON2 0x24c
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/*
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* | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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* CS0: | Mode | d | c | b | a |
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* CS1: | Category Code |
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* CS2: | Channel Number | Source Number |
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* CS3: | Clock Accuracy | Sample Freq |
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* CS4: | Ori Sample Freq | Word Length |
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* CS5: | | CGMS-A |
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* CS6~CS23: Reserved
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*
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* a: use of channel status block
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* b: linear PCM identification: 0 for lpcm, 1 for nlpcm
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* c: copyright information
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* d: additional format information
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*/
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#define CS_BYTE 6
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#define CS_FRAME(c) ((c) << 16 | (c))
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#define RK3288_GRF_SOC_CON2 0x24c
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struct rk_spdif_dev {
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struct device *dev;
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@ -40,29 +60,6 @@ struct rk_spdif_dev {
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struct regmap *regmap;
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};
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static const struct of_device_id rk_spdif_match[] __maybe_unused = {
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{ .compatible = "rockchip,rk3066-spdif",
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.data = (void *)RK_SPDIF_RK3066 },
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{ .compatible = "rockchip,rk3188-spdif",
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.data = (void *)RK_SPDIF_RK3188 },
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{ .compatible = "rockchip,rk3228-spdif",
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.data = (void *)RK_SPDIF_RK3366 },
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{ .compatible = "rockchip,rk3288-spdif",
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.data = (void *)RK_SPDIF_RK3288 },
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{ .compatible = "rockchip,rk3328-spdif",
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.data = (void *)RK_SPDIF_RK3366 },
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{ .compatible = "rockchip,rk3366-spdif",
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.data = (void *)RK_SPDIF_RK3366 },
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{ .compatible = "rockchip,rk3368-spdif",
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.data = (void *)RK_SPDIF_RK3366 },
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{ .compatible = "rockchip,rk3399-spdif",
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.data = (void *)RK_SPDIF_RK3366 },
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{ .compatible = "rockchip,rk3568-spdif",
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.data = (void *)RK_SPDIF_RK3366 },
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{},
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};
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MODULE_DEVICE_TABLE(of, rk_spdif_match);
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static int rk_spdif_runtime_suspend(struct device *dev)
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{
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struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
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@ -109,39 +106,63 @@ static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
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unsigned int mclk_rate = clk_get_rate(spdif->mclk);
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unsigned int val = SPDIF_CFGR_HALFWORD_ENABLE;
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int srate, mclk;
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int ret;
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int bmc, div, ret, i;
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u16 *fc;
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u8 cs[CS_BYTE];
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srate = params_rate(params);
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mclk = srate * 128;
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ret = snd_pcm_create_iec958_consumer_hw_params(params, cs, sizeof(cs));
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if (ret < 0)
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return ret;
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fc = (u16 *)cs;
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for (i = 0; i < CS_BYTE / 2; i++)
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regmap_write(spdif->regmap, SPDIF_CHNSRn(i), CS_FRAME(fc[i]));
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regmap_update_bits(spdif->regmap, SPDIF_CFGR, SPDIF_CFGR_CSE_MASK,
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SPDIF_CFGR_CSE_EN);
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/* bmc = 128fs */
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bmc = 128 * params_rate(params);
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div = DIV_ROUND_CLOSEST(mclk_rate, bmc);
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val |= SPDIF_CFGR_CLK_DIV(div);
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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val |= SPDIF_CFGR_VDW_16;
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val |= SPDIF_CFGR_ADJ_RIGHT_J;
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break;
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case SNDRV_PCM_FORMAT_S20_3LE:
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val |= SPDIF_CFGR_VDW_20;
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val |= SPDIF_CFGR_ADJ_RIGHT_J;
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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val |= SPDIF_CFGR_VDW_24;
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val |= SPDIF_CFGR_ADJ_RIGHT_J;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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val |= SPDIF_CFGR_VDW_24;
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val |= SPDIF_CFGR_ADJ_LEFT_J;
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break;
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default:
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return -EINVAL;
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}
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/* Set clock and calculate divider */
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ret = clk_set_rate(spdif->mclk, mclk);
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if (ret != 0) {
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dev_err(spdif->dev, "Failed to set module clock rate: %d\n",
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ret);
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return ret;
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}
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/*
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* clear MCLK domain logic before setting Fmclk and Fsdo to ensure
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* that switching between S16_LE and S32_LE audio does not result
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* in accidential channels swap.
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*/
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regmap_update_bits(spdif->regmap, SPDIF_CFGR, SPDIF_CFGR_CLR_MASK,
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SPDIF_CFGR_CLR_EN);
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udelay(1);
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ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,
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SPDIF_CFGR_CLK_DIV_MASK |
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SPDIF_CFGR_HALFWORD_ENABLE |
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SDPIF_CFGR_VDW_MASK, val);
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SPDIF_CFGR_HALFWORD_MASK |
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SDPIF_CFGR_VDW_MASK |
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SPDIF_CFGR_ADJ_MASK, val);
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return ret;
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}
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@ -157,7 +178,7 @@ static int rk_spdif_trigger(struct snd_pcm_substream *substream,
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
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SPDIF_DMACR_TDE_ENABLE |
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SPDIF_DMACR_TDE_MASK |
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SPDIF_DMACR_TDL_MASK,
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SPDIF_DMACR_TDE_ENABLE |
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SPDIF_DMACR_TDL(16));
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@ -166,21 +187,21 @@ static int rk_spdif_trigger(struct snd_pcm_substream *substream,
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return ret;
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ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
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SPDIF_XFER_TXS_START,
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SPDIF_XFER_TXS_MASK,
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SPDIF_XFER_TXS_START);
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break;
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
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SPDIF_DMACR_TDE_ENABLE,
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SPDIF_DMACR_TDE_MASK,
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SPDIF_DMACR_TDE_DISABLE);
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if (ret != 0)
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return ret;
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ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
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SPDIF_XFER_TXS_START,
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SPDIF_XFER_TXS_MASK,
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SPDIF_XFER_TXS_STOP);
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break;
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default:
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@ -200,7 +221,24 @@ static int rk_spdif_dai_probe(struct snd_soc_dai *dai)
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return 0;
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}
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static int rk_spdif_set_sysclk(struct snd_soc_dai *dai,
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int clk_id, unsigned int freq, int dir)
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{
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struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
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int ret;
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if (!freq)
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return 0;
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ret = clk_set_rate(spdif->mclk, freq);
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if (ret)
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dev_err(spdif->dev, "Failed to set mclk: %d\n", ret);
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return ret;
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}
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static const struct snd_soc_dai_ops rk_spdif_dai_ops = {
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.set_sysclk = rk_spdif_set_sysclk,
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.probe = rk_spdif_dai_probe,
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.hw_params = rk_spdif_hw_params,
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.trigger = rk_spdif_trigger,
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@ -211,14 +249,11 @@ static struct snd_soc_dai_driver rk_spdif_dai = {
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.stream_name = "Playback",
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.channels_min = 2,
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.channels_max = 2,
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.rates = (SNDRV_PCM_RATE_32000 |
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SNDRV_PCM_RATE_44100 |
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SNDRV_PCM_RATE_48000 |
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SNDRV_PCM_RATE_96000 |
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SNDRV_PCM_RATE_192000),
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.rates = SNDRV_PCM_RATE_8000_192000,
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.formats = (SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S20_3LE |
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SNDRV_PCM_FMTBIT_S24_LE),
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SNDRV_PCM_FMTBIT_S24_LE |
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SNDRV_PCM_FMTBIT_S32_LE),
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},
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.ops = &rk_spdif_dai_ops,
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};
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@ -236,6 +271,9 @@ static bool rk_spdif_wr_reg(struct device *dev, unsigned int reg)
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case SPDIF_INTCR:
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case SPDIF_XFER:
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case SPDIF_SMPDR:
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case SPDIF_VLDFRn(0) ... SPDIF_VLDFRn(11):
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case SPDIF_USRDRn(0) ... SPDIF_USRDRn(11):
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case SPDIF_CHNSRn(0) ... SPDIF_CHNSRn(11):
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return true;
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default:
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return false;
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@ -251,6 +289,9 @@ static bool rk_spdif_rd_reg(struct device *dev, unsigned int reg)
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case SPDIF_INTSR:
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case SPDIF_XFER:
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case SPDIF_SMPDR:
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case SPDIF_VLDFRn(0) ... SPDIF_VLDFRn(11):
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case SPDIF_USRDRn(0) ... SPDIF_USRDRn(11):
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case SPDIF_CHNSRn(0) ... SPDIF_CHNSRn(11):
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return true;
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default:
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return false;
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@ -273,32 +314,38 @@ static const struct regmap_config rk_spdif_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = SPDIF_SMPDR,
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.max_register = SPDIF_VERSION,
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.writeable_reg = rk_spdif_wr_reg,
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.readable_reg = rk_spdif_rd_reg,
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.volatile_reg = rk_spdif_volatile_reg,
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.cache_type = REGCACHE_FLAT,
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};
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static void rk_spdif_suspend(void *data)
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{
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struct device *dev = data;
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if (!pm_runtime_status_suspended(dev))
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rk_spdif_runtime_suspend(dev);
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}
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static int rk_spdif_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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enum rk_spdif_type spdif_type;
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struct rk_spdif_dev *spdif;
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const struct of_device_id *match;
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struct resource *res;
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void __iomem *regs;
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int ret;
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match = of_match_node(rk_spdif_match, np);
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if (match->data == (void *)RK_SPDIF_RK3288) {
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spdif_type = (uintptr_t) device_get_match_data(&pdev->dev);
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if (spdif_type == RK_SPDIF_RK3288) {
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struct regmap *grf;
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grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
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if (IS_ERR(grf)) {
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dev_err(&pdev->dev,
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if (IS_ERR(grf))
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return dev_err_probe(&pdev->dev, PTR_ERR(grf),
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"rockchip_spdif missing 'rockchip,grf'\n");
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return PTR_ERR(grf);
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}
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/* Select the 8 channel SPDIF solution on RK3288 as
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* the 2 channel one does not appear to work
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@ -334,55 +381,63 @@ static int rk_spdif_probe(struct platform_device *pdev)
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spdif->dev = &pdev->dev;
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dev_set_drvdata(&pdev->dev, spdif);
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pm_runtime_enable(&pdev->dev);
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ret = devm_add_action_or_reset(&pdev->dev, rk_spdif_suspend, &pdev->dev);
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if (ret)
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return ret;
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devm_pm_runtime_enable(&pdev->dev);
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if (!pm_runtime_enabled(&pdev->dev)) {
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ret = rk_spdif_runtime_resume(&pdev->dev);
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if (ret)
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goto err_pm_runtime;
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return ret;
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}
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ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
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if (ret)
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return dev_err_probe(&pdev->dev, ret, "Could not register PCM\n");
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ret = devm_snd_soc_register_component(&pdev->dev,
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&rk_spdif_component,
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&rk_spdif_dai, 1);
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if (ret) {
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dev_err(&pdev->dev, "Could not register DAI\n");
|
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goto err_pm_suspend;
|
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}
|
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|
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ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
|
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if (ret) {
|
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dev_err(&pdev->dev, "Could not register PCM\n");
|
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goto err_pm_suspend;
|
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}
|
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if (ret)
|
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return dev_err_probe(&pdev->dev, ret, "Could not register DAI\n");
|
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return 0;
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|
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err_pm_suspend:
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if (!pm_runtime_status_suspended(&pdev->dev))
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rk_spdif_runtime_suspend(&pdev->dev);
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err_pm_runtime:
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pm_runtime_disable(&pdev->dev);
|
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return ret;
|
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}
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|
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static void rk_spdif_remove(struct platform_device *pdev)
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{
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pm_runtime_disable(&pdev->dev);
|
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if (!pm_runtime_status_suspended(&pdev->dev))
|
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rk_spdif_runtime_suspend(&pdev->dev);
|
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}
|
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|
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static const struct dev_pm_ops rk_spdif_pm_ops = {
|
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RUNTIME_PM_OPS(rk_spdif_runtime_suspend, rk_spdif_runtime_resume, NULL)
|
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};
|
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|
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static const struct of_device_id rk_spdif_match[] = {
|
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{ .compatible = "rockchip,rk3066-spdif",
|
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.data = (void *)RK_SPDIF_RK3066 },
|
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{ .compatible = "rockchip,rk3188-spdif",
|
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.data = (void *)RK_SPDIF_RK3188 },
|
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{ .compatible = "rockchip,rk3228-spdif",
|
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.data = (void *)RK_SPDIF_RK3366 },
|
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{ .compatible = "rockchip,rk3288-spdif",
|
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.data = (void *)RK_SPDIF_RK3288 },
|
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{ .compatible = "rockchip,rk3328-spdif",
|
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.data = (void *)RK_SPDIF_RK3366 },
|
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{ .compatible = "rockchip,rk3366-spdif",
|
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.data = (void *)RK_SPDIF_RK3366 },
|
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{ .compatible = "rockchip,rk3368-spdif",
|
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.data = (void *)RK_SPDIF_RK3366 },
|
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{ .compatible = "rockchip,rk3399-spdif",
|
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.data = (void *)RK_SPDIF_RK3366 },
|
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{ .compatible = "rockchip,rk3568-spdif",
|
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.data = (void *)RK_SPDIF_RK3366 },
|
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{},
|
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};
|
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MODULE_DEVICE_TABLE(of, rk_spdif_match);
|
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|
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static struct platform_driver rk_spdif_driver = {
|
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.probe = rk_spdif_probe,
|
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.remove = rk_spdif_remove,
|
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.driver = {
|
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.name = "rockchip-spdif",
|
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.of_match_table = of_match_ptr(rk_spdif_match),
|
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.of_match_table = rk_spdif_match,
|
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.pm = pm_ptr(&rk_spdif_pm_ops),
|
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},
|
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};
|
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|
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|||
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@ -2,7 +2,7 @@
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/*
|
||||
* ALSA SoC Audio Layer - Rockchip SPDIF transceiver driver
|
||||
*
|
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* Copyright (c) 2015 Collabora Ltd.
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* Copyright (c) 2015-2026 Collabora Ltd.
|
||||
* Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
|
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*/
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|
|
@ -13,41 +13,50 @@
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|||
* CFGR
|
||||
* transfer configuration register
|
||||
*/
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#define SPDIF_CFGR_CLK_DIV_SHIFT (16)
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#define SPDIF_CFGR_CLK_DIV_MASK (0xff << SPDIF_CFGR_CLK_DIV_SHIFT)
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#define SPDIF_CFGR_CLK_DIV(x) (x << SPDIF_CFGR_CLK_DIV_SHIFT)
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#define SPDIF_CFGR_CLK_DIV_MASK GENMASK(23, 16)
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#define SPDIF_CFGR_CLK_DIV(x) FIELD_PREP(SPDIF_CFGR_CLK_DIV_MASK, x-1)
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||||
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#define SPDIF_CFGR_HALFWORD_SHIFT 2
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#define SPDIF_CFGR_HALFWORD_DISABLE (0 << SPDIF_CFGR_HALFWORD_SHIFT)
|
||||
#define SPDIF_CFGR_HALFWORD_ENABLE (1 << SPDIF_CFGR_HALFWORD_SHIFT)
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#define SPDIF_CFGR_CLR_MASK BIT(7)
|
||||
#define SPDIF_CFGR_CLR_EN FIELD_PREP(SPDIF_CFGR_CLR_MASK, 1)
|
||||
#define SPDIF_CFGR_CLR_DIS FIELD_PREP(SPDIF_CFGR_CLR_MASK, 0)
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||||
|
||||
#define SPDIF_CFGR_VDW_SHIFT 0
|
||||
#define SPDIF_CFGR_VDW(x) (x << SPDIF_CFGR_VDW_SHIFT)
|
||||
#define SDPIF_CFGR_VDW_MASK (0xf << SPDIF_CFGR_VDW_SHIFT)
|
||||
#define SPDIF_CFGR_CSE_MASK BIT(6)
|
||||
#define SPDIF_CFGR_CSE_EN FIELD_PREP(SPDIF_CFGR_CSE_MASK, 1)
|
||||
#define SPDIF_CFGR_CSE_DIS FIELD_PREP(SPDIF_CFGR_CSE_MASK, 0)
|
||||
|
||||
#define SPDIF_CFGR_VDW_16 SPDIF_CFGR_VDW(0x0)
|
||||
#define SPDIF_CFGR_VDW_20 SPDIF_CFGR_VDW(0x1)
|
||||
#define SPDIF_CFGR_VDW_24 SPDIF_CFGR_VDW(0x2)
|
||||
#define SPDIF_CFGR_ADJ_MASK BIT(3)
|
||||
#define SPDIF_CFGR_ADJ_LEFT_J FIELD_PREP(SPDIF_CFGR_ADJ_MASK, 1)
|
||||
#define SPDIF_CFGR_ADJ_RIGHT_J FIELD_PREP(SPDIF_CFGR_ADJ_MASK, 0)
|
||||
|
||||
#define SPDIF_CFGR_HALFWORD_MASK BIT(2)
|
||||
#define SPDIF_CFGR_HALFWORD_DISABLE FIELD_PREP(SPDIF_CFGR_HALFWORD_MASK, 0)
|
||||
#define SPDIF_CFGR_HALFWORD_ENABLE FIELD_PREP(SPDIF_CFGR_HALFWORD_MASK, 1)
|
||||
|
||||
#define SDPIF_CFGR_VDW_MASK GENMASK(1, 0)
|
||||
#define SPDIF_CFGR_VDW(x) FIELD_PREP(SDPIF_CFGR_VDW_MASK, x)
|
||||
|
||||
#define SPDIF_CFGR_VDW_16 SPDIF_CFGR_VDW(0x0)
|
||||
#define SPDIF_CFGR_VDW_20 SPDIF_CFGR_VDW(0x1)
|
||||
#define SPDIF_CFGR_VDW_24 SPDIF_CFGR_VDW(0x2)
|
||||
|
||||
/*
|
||||
* DMACR
|
||||
* DMA control register
|
||||
*/
|
||||
#define SPDIF_DMACR_TDE_SHIFT 5
|
||||
#define SPDIF_DMACR_TDE_DISABLE (0 << SPDIF_DMACR_TDE_SHIFT)
|
||||
#define SPDIF_DMACR_TDE_ENABLE (1 << SPDIF_DMACR_TDE_SHIFT)
|
||||
#define SPDIF_DMACR_TDE_MASK BIT(5)
|
||||
#define SPDIF_DMACR_TDE_DISABLE FIELD_PREP(SPDIF_DMACR_TDE_MASK, 0)
|
||||
#define SPDIF_DMACR_TDE_ENABLE FIELD_PREP(SPDIF_DMACR_TDE_MASK, 1)
|
||||
|
||||
#define SPDIF_DMACR_TDL_SHIFT 0
|
||||
#define SPDIF_DMACR_TDL(x) ((x) << SPDIF_DMACR_TDL_SHIFT)
|
||||
#define SPDIF_DMACR_TDL_MASK (0x1f << SPDIF_DMACR_TDL_SHIFT)
|
||||
#define SPDIF_DMACR_TDL_MASK GENMASK(4, 0)
|
||||
#define SPDIF_DMACR_TDL(x) FIELD_PREP(SPDIF_DMACR_TDL_MASK, x)
|
||||
|
||||
/*
|
||||
* XFER
|
||||
* Transfer control register
|
||||
*/
|
||||
#define SPDIF_XFER_TXS_SHIFT 0
|
||||
#define SPDIF_XFER_TXS_STOP (0 << SPDIF_XFER_TXS_SHIFT)
|
||||
#define SPDIF_XFER_TXS_START (1 << SPDIF_XFER_TXS_SHIFT)
|
||||
#define SPDIF_XFER_TXS_MASK BIT(0)
|
||||
#define SPDIF_XFER_TXS_STOP FIELD_PREP(SPDIF_XFER_TXS_MASK, 0)
|
||||
#define SPDIF_XFER_TXS_START FIELD_PREP(SPDIF_XFER_TXS_MASK, 1)
|
||||
|
||||
#define SPDIF_CFGR (0x0000)
|
||||
#define SPDIF_SDBLR (0x0004)
|
||||
|
|
@ -56,5 +65,9 @@
|
|||
#define SPDIF_INTSR (0x0010)
|
||||
#define SPDIF_XFER (0x0018)
|
||||
#define SPDIF_SMPDR (0x0020)
|
||||
#define SPDIF_VLDFRn(x) (0x0060 + (x) * 4)
|
||||
#define SPDIF_USRDRn(x) (0x0090 + (x) * 4)
|
||||
#define SPDIF_CHNSRn(x) (0x00c0 + (x) * 4)
|
||||
#define SPDIF_VERSION (0x01c0)
|
||||
|
||||
#endif /* _ROCKCHIP_SPDIF_H */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue