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KVM: arm64: nv: Map VNCR-capable registers to a separate page
With ARMv8.4-NV, registers that can be directly accessed in memory by the guest have to live at architected offsets in a special page. Let's annotate the sysreg enum to reflect the offset at which they are in this page, whith a little twist: If running on HW that doesn't have the ARMv8.4-NV feature, or even a VM that doesn't use NV, we store all the system registers in the usual sys_regs array. The only difference with the pre-8.4 situation is that VNCR-capable registers are at a "similar" offset as in the VNCR page (we can compute the actual offset at compile time), and that the sys_regs array is both bigger and sparse. Reviewed-by: Oliver Upton <oliver.upton@linux.dev> Signed-off-by: Marc Zyngier <maz@kernel.org>
This commit is contained in:
Marc Zyngier
parent
9b9cce60be
commit
d8bd48e3f0
1 changed files with 81 additions and 46 deletions
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@ -27,6 +27,7 @@
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#include <asm/fpsimd.h>
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#include <asm/kvm.h>
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#include <asm/kvm_asm.h>
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#include <asm/vncr_mapping.h>
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#define __KVM_HAVE_ARCH_INTC_INITIALIZED
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@ -325,33 +326,33 @@ struct kvm_vcpu_fault_info {
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u64 disr_el1; /* Deferred [SError] Status Register */
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};
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/*
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* VNCR() just places the VNCR_capable registers in the enum after
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* __VNCR_START__, and the value (after correction) to be an 8-byte offset
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* from the VNCR base. As we don't require the enum to be otherwise ordered,
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* we need the terrible hack below to ensure that we correctly size the
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* sys_regs array, no matter what.
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*
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* The __MAX__ macro has been lifted from Sean Eron Anderson's wonderful
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* treasure trove of bit hacks:
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* https://graphics.stanford.edu/~seander/bithacks.html#IntegerMinOrMax
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*/
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#define __MAX__(x,y) ((x) ^ (((x) ^ (y)) & -((x) < (y))))
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#define VNCR(r) \
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__before_##r, \
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r = __VNCR_START__ + ((VNCR_ ## r) / 8), \
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__after_##r = __MAX__(__before_##r - 1, r)
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enum vcpu_sysreg {
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__INVALID_SYSREG__, /* 0 is reserved as an invalid value */
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MPIDR_EL1, /* MultiProcessor Affinity Register */
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CLIDR_EL1, /* Cache Level ID Register */
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CSSELR_EL1, /* Cache Size Selection Register */
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SCTLR_EL1, /* System Control Register */
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ACTLR_EL1, /* Auxiliary Control Register */
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CPACR_EL1, /* Coprocessor Access Control */
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ZCR_EL1, /* SVE Control */
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TTBR0_EL1, /* Translation Table Base Register 0 */
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TTBR1_EL1, /* Translation Table Base Register 1 */
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TCR_EL1, /* Translation Control Register */
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TCR2_EL1, /* Extended Translation Control Register */
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ESR_EL1, /* Exception Syndrome Register */
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AFSR0_EL1, /* Auxiliary Fault Status Register 0 */
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AFSR1_EL1, /* Auxiliary Fault Status Register 1 */
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FAR_EL1, /* Fault Address Register */
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MAIR_EL1, /* Memory Attribute Indirection Register */
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VBAR_EL1, /* Vector Base Address Register */
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CONTEXTIDR_EL1, /* Context ID Register */
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TPIDR_EL0, /* Thread ID, User R/W */
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TPIDRRO_EL0, /* Thread ID, User R/O */
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TPIDR_EL1, /* Thread ID, Privileged */
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AMAIR_EL1, /* Aux Memory Attribute Indirection Register */
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CNTKCTL_EL1, /* Timer Control Register (EL1) */
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PAR_EL1, /* Physical Address Register */
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MDSCR_EL1, /* Monitor Debug System Control Register */
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MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
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OSLSR_EL1, /* OS Lock Status Register */
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DISR_EL1, /* Deferred Interrupt Status Register */
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@ -382,26 +383,11 @@ enum vcpu_sysreg {
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APGAKEYLO_EL1,
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APGAKEYHI_EL1,
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ELR_EL1,
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SP_EL1,
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SPSR_EL1,
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CNTVOFF_EL2,
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CNTV_CVAL_EL0,
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CNTV_CTL_EL0,
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CNTP_CVAL_EL0,
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CNTP_CTL_EL0,
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/* Memory Tagging Extension registers */
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RGSR_EL1, /* Random Allocation Tag Seed Register */
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GCR_EL1, /* Tag Control Register */
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TFSR_EL1, /* Tag Fault Status Register (EL1) */
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TFSRE0_EL1, /* Tag Fault Status Register (EL0) */
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/* Permission Indirection Extension registers */
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PIR_EL1, /* Permission Indirection Register 1 (EL1) */
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PIRE0_EL1, /* Permission Indirection Register 0 (EL1) */
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/* 32bit specific registers. */
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DACR32_EL2, /* Domain Access Control Register */
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IFSR32_EL2, /* Instruction Fault Status Register */
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@ -409,21 +395,14 @@ enum vcpu_sysreg {
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DBGVCR32_EL2, /* Debug Vector Catch Register */
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/* EL2 registers */
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VPIDR_EL2, /* Virtualization Processor ID Register */
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VMPIDR_EL2, /* Virtualization Multiprocessor ID Register */
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SCTLR_EL2, /* System Control Register (EL2) */
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ACTLR_EL2, /* Auxiliary Control Register (EL2) */
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HCR_EL2, /* Hypervisor Configuration Register */
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MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */
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CPTR_EL2, /* Architectural Feature Trap Register (EL2) */
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HSTR_EL2, /* Hypervisor System Trap Register */
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HACR_EL2, /* Hypervisor Auxiliary Control Register */
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HCRX_EL2, /* Extended Hypervisor Configuration Register */
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TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */
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TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */
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TCR_EL2, /* Translation Control Register (EL2) */
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VTTBR_EL2, /* Virtualization Translation Table Base Register */
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VTCR_EL2, /* Virtualization Translation Control Register */
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SPSR_EL2, /* EL2 saved program status register */
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ELR_EL2, /* EL2 exception link register */
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AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */
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@ -436,19 +415,61 @@ enum vcpu_sysreg {
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VBAR_EL2, /* Vector Base Address Register (EL2) */
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RVBAR_EL2, /* Reset Vector Base Address Register */
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CONTEXTIDR_EL2, /* Context ID Register (EL2) */
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TPIDR_EL2, /* EL2 Software Thread ID Register */
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CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */
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SP_EL2, /* EL2 Stack Pointer */
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HFGRTR_EL2,
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HFGWTR_EL2,
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HFGITR_EL2,
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HDFGRTR_EL2,
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HDFGWTR_EL2,
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CNTHP_CTL_EL2,
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CNTHP_CVAL_EL2,
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CNTHV_CTL_EL2,
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CNTHV_CVAL_EL2,
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__VNCR_START__, /* Any VNCR-capable reg goes after this point */
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VNCR(SCTLR_EL1),/* System Control Register */
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VNCR(ACTLR_EL1),/* Auxiliary Control Register */
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VNCR(CPACR_EL1),/* Coprocessor Access Control */
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VNCR(ZCR_EL1), /* SVE Control */
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VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */
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VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */
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VNCR(TCR_EL1), /* Translation Control Register */
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VNCR(TCR2_EL1), /* Extended Translation Control Register */
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VNCR(ESR_EL1), /* Exception Syndrome Register */
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VNCR(AFSR0_EL1),/* Auxiliary Fault Status Register 0 */
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VNCR(AFSR1_EL1),/* Auxiliary Fault Status Register 1 */
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VNCR(FAR_EL1), /* Fault Address Register */
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VNCR(MAIR_EL1), /* Memory Attribute Indirection Register */
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VNCR(VBAR_EL1), /* Vector Base Address Register */
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VNCR(CONTEXTIDR_EL1), /* Context ID Register */
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VNCR(AMAIR_EL1),/* Aux Memory Attribute Indirection Register */
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VNCR(MDSCR_EL1),/* Monitor Debug System Control Register */
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VNCR(ELR_EL1),
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VNCR(SP_EL1),
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VNCR(SPSR_EL1),
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VNCR(TFSR_EL1), /* Tag Fault Status Register (EL1) */
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VNCR(VPIDR_EL2),/* Virtualization Processor ID Register */
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VNCR(VMPIDR_EL2),/* Virtualization Multiprocessor ID Register */
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VNCR(HCR_EL2), /* Hypervisor Configuration Register */
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VNCR(HSTR_EL2), /* Hypervisor System Trap Register */
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VNCR(VTTBR_EL2),/* Virtualization Translation Table Base Register */
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VNCR(VTCR_EL2), /* Virtualization Translation Control Register */
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VNCR(TPIDR_EL2),/* EL2 Software Thread ID Register */
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VNCR(HCRX_EL2), /* Extended Hypervisor Configuration Register */
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/* Permission Indirection Extension registers */
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VNCR(PIR_EL1), /* Permission Indirection Register 1 (EL1) */
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VNCR(PIRE0_EL1), /* Permission Indirection Register 0 (EL1) */
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VNCR(HFGRTR_EL2),
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VNCR(HFGWTR_EL2),
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VNCR(HFGITR_EL2),
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VNCR(HDFGRTR_EL2),
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VNCR(HDFGWTR_EL2),
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VNCR(CNTVOFF_EL2),
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VNCR(CNTV_CVAL_EL0),
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VNCR(CNTV_CTL_EL0),
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VNCR(CNTP_CVAL_EL0),
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VNCR(CNTP_CTL_EL0),
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NR_SYS_REGS /* Nothing after this line! */
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};
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@ -465,6 +486,9 @@ struct kvm_cpu_context {
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u64 sys_regs[NR_SYS_REGS];
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struct kvm_vcpu *__hyp_running_vcpu;
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/* This pointer has to be 4kB aligned. */
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u64 *vncr_array;
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};
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struct kvm_host_data {
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@ -827,8 +851,19 @@ struct kvm_vcpu_arch {
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* accessed by a running VCPU. For example, for userspace access or
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* for system registers that are never context switched, but only
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* emulated.
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*
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* Don't bother with VNCR-based accesses in the nVHE code, it has no
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* business dealing with NV.
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*/
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#define __ctxt_sys_reg(c,r) (&(c)->sys_regs[(r)])
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static inline u64 *__ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r)
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{
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#if !defined (__KVM_NVHE_HYPERVISOR__)
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if (unlikely(cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) &&
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r >= __VNCR_START__ && ctxt->vncr_array))
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return &ctxt->vncr_array[r - __VNCR_START__];
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#endif
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return (u64 *)&ctxt->sys_regs[r];
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}
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#define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r))
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