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clk: renesas: r8a779g0: Add ISP core clocks

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Add the ISP core modules clock for Renesas R-Car V4H.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250114183005.2761213-3-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Niklas Söderlund 2025-01-14 19:30:04 +01:00 • committed by Geert Uytterhoeven
parent 3b0016a613
commit d871a94062
1 changed files with 2 additions and 0 deletions
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drivers/clk/renesas/r8a779g0-cpg-mssr.c
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@ -163,6 +163,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
};
static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
DEF_MOD("isp0", 16, R8A779G0_CLK_S0D2_VIO),
DEF_MOD("isp1", 17, R8A779G0_CLK_S0D2_VIO),
DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC),
DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC),
DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC),