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drm/xe/xe_hw_error: Add fault injection to trigger csc error handler
Add a debugfs fault handler to trigger csc error handler that wedges the device and enables runtime survivability mode. v2: add debugfs only for bmg (Umesh) v3: do not use csc_fault attribute if debugfs is not enabled v4: rebase Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Riana Tauro <riana.tauro@intel.com> Reviewed-by: Raag Jadav <raag.jadav@intel.com> Link: https://lore.kernel.org/r/20250826063419.3022216-11-riana.tauro@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2 changed files with 16 additions and 1 deletions
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@ -35,6 +35,7 @@
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#endif
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DECLARE_FAULT_ATTR(gt_reset_failure);
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DECLARE_FAULT_ATTR(inject_csc_hw_error);
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static void read_residency_counter(struct xe_device *xe, struct xe_mmio *mmio,
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u32 offset, char *name, struct drm_printer *p)
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@ -361,10 +362,13 @@ void xe_debugfs_register(struct xe_device *xe)
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ARRAY_SIZE(debugfs_list),
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root, minor);
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if (xe->info.platform == XE_BATTLEMAGE)
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if (xe->info.platform == XE_BATTLEMAGE) {
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drm_debugfs_create_files(debugfs_residencies,
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ARRAY_SIZE(debugfs_residencies),
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root, minor);
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fault_create_debugfs_attr("inject_csc_hw_error", root,
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&inject_csc_hw_error);
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}
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debugfs_create_file("forcewake_all", 0400, root, xe,
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&forcewake_all_fops);
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@ -3,6 +3,8 @@
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* Copyright © 2025 Intel Corporation
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*/
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#include <linux/fault-inject.h>
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#include "regs/xe_gsc_regs.h"
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#include "regs/xe_hw_error_regs.h"
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#include "regs/xe_irq_regs.h"
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@ -13,6 +15,7 @@
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#include "xe_survivability_mode.h"
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#define HEC_UNCORR_FW_ERR_BITS 4
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extern struct fault_attr inject_csc_hw_error;
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/* Error categories reported by hardware */
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enum hardware_error {
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@ -43,6 +46,11 @@ static const char *hw_error_to_str(const enum hardware_error hw_err)
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}
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}
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static bool fault_inject_csc_hw_error(void)
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{
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return IS_ENABLED(CONFIG_DEBUG_FS) && should_fail(&inject_csc_hw_error, 1);
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}
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static void csc_hw_error_work(struct work_struct *work)
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{
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struct xe_tile *tile = container_of(work, typeof(*tile), csc_hw_error_work);
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@ -130,6 +138,9 @@ void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl)
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{
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enum hardware_error hw_err;
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if (fault_inject_csc_hw_error())
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schedule_work(&tile->csc_hw_error_work);
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for (hw_err = 0; hw_err < HARDWARE_ERROR_MAX; hw_err++)
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if (master_ctl & ERROR_IRQ(hw_err))
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hw_error_source_handler(tile, hw_err);
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