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pinctrl: renesas: rzg2l: Unify OEN handling across RZ/{G2L,V2H,V2N}
Unify the OEN handling on RZ/V2H(P) and RZ/V2N SoCs by reusing the existing rzg2l_read_oen and rzg2l_write_oen functions from RZ/G2L. Add a pin_to_oen_bit callback in rzg2l_pinctrl_data to look up per-pin OEN bit positions, and introduce an oen_pwpr_lock flag in the hwcfg to manage PWPR locking on SoCs that require it (RZ/V2H(P) family). Remove the hardcoded PFC_OEN define and obsolete per-SoC OEN helpers. Also drop redundant checks for the OEN offset in the suspend/resume paths, as all supported SoCs now provide a valid offset through the `regs.oen` field. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250806195555.1372317-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar
Geert Uytterhoeven
parent
dd0d40d8f4
commit
cd39805be8
1 changed files with 22 additions and 46 deletions
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@ -146,7 +146,6 @@
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#define SD_CH(off, ch) ((off) + (ch) * 4)
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#define ETH_POC(off, ch) ((off) + (ch) * 4)
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#define QSPI (0x3008)
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#define PFC_OEN (0x3C40) /* known on RZ/V2H(P) only */
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#define PVDD_2500 2 /* I/O domain voltage 2.5V */
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#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
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@ -255,6 +254,7 @@ enum rzg2l_iolh_index {
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* @iolh_groupb_oi: IOLH group B output impedance specific values
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* @tint_start_index: the start index for the TINT interrupts
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* @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported)
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* @oen_pwpr_lock: flag indicating if the OEN register is locked by PWPR
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* @func_base: base number for port function (see register PFC)
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* @oen_max_pin: the maximum pin number supporting output enable
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* @oen_max_port: the maximum port number supporting output enable
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@ -267,6 +267,7 @@ struct rzg2l_hwcfg {
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u16 iolh_groupb_oi[4];
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u16 tint_start_index;
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bool drive_strength_ua;
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bool oen_pwpr_lock;
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u8 func_base;
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u8 oen_max_pin;
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u8 oen_max_port;
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@ -1083,10 +1084,11 @@ static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
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static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
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{
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const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
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u16 oen_offset = pctrl->data->hwcfg->regs.oen;
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unsigned long flags;
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u8 val, pwpr;
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int bit;
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u8 val;
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if (!pctrl->data->pin_to_oen_bit)
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return -EINVAL;
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@ -1101,7 +1103,13 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oe
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val &= ~BIT(bit);
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else
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val |= BIT(bit);
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if (pctrl->data->hwcfg->oen_pwpr_lock) {
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pwpr = readb(pctrl->base + regs->pwpr);
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writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);
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}
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writeb(val, pctrl->base + oen_offset);
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if (pctrl->data->hwcfg->oen_pwpr_lock)
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writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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return 0;
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@ -1192,7 +1200,7 @@ static int rzv2h_bias_param_to_hw(enum pin_config_param param)
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return -EINVAL;
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}
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static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
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static int rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
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{
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static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK",
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"XSPI0_RESET0N", "XSPI0_CS0N",
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@ -1206,41 +1214,7 @@ static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
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}
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/* Should not happen. */
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return 0;
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}
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static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
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{
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u8 bit;
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bit = rzv2h_pin_to_oen_bit(pctrl, _pin);
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return !(readb(pctrl->base + PFC_OEN) & BIT(bit));
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}
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static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
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{
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const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
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const struct rzg2l_register_offsets *regs = &hwcfg->regs;
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unsigned long flags;
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u8 val, bit;
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u8 pwpr;
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bit = rzv2h_pin_to_oen_bit(pctrl, _pin);
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spin_lock_irqsave(&pctrl->lock, flags);
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val = readb(pctrl->base + PFC_OEN);
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if (oen)
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val &= ~BIT(bit);
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else
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val |= BIT(bit);
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pwpr = readb(pctrl->base + regs->pwpr);
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writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);
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writeb(val, pctrl->base + PFC_OEN);
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writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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return 0;
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return -EINVAL;
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}
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static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
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@ -3140,8 +3114,7 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
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}
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cache->qspi = readb(pctrl->base + QSPI);
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if (pctrl->data->hwcfg->regs.oen)
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cache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen);
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cache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen);
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if (!atomic_read(&pctrl->wakeup_path))
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clk_disable_unprepare(pctrl->clk);
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@ -3166,8 +3139,7 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev)
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}
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writeb(cache->qspi, pctrl->base + QSPI);
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if (pctrl->data->hwcfg->regs.oen)
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writeb(cache->oen, pctrl->base + pctrl->data->hwcfg->regs.oen);
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writeb(cache->oen, pctrl->base + pctrl->data->hwcfg->regs.oen);
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for (u8 i = 0; i < 2; i++) {
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if (regs->sd_ch)
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writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i));
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@ -3267,8 +3239,10 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = {
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static const struct rzg2l_hwcfg rzv2h_hwcfg = {
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.regs = {
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.pwpr = 0x3c04,
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.oen = 0x3c40,
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},
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.tint_start_index = 17,
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.oen_pwpr_lock = true,
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};
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static struct rzg2l_pinctrl_data r9a07g043_data = {
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@ -3365,8 +3339,9 @@ static struct rzg2l_pinctrl_data r9a09g056_data = {
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#endif
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.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
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.pmc_writeb = &rzv2h_pmc_writeb,
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.oen_read = &rzv2h_oen_read,
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.oen_write = &rzv2h_oen_write,
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.pin_to_oen_bit = &rzv2h_pin_to_oen_bit,
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.oen_read = &rzg2l_read_oen,
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.oen_write = &rzg2l_write_oen,
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.hw_to_bias_param = &rzv2h_hw_to_bias_param,
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.bias_param_to_hw = &rzv2h_bias_param_to_hw,
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};
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@ -3389,8 +3364,9 @@ static struct rzg2l_pinctrl_data r9a09g057_data = {
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#endif
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.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
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.pmc_writeb = &rzv2h_pmc_writeb,
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.oen_read = &rzv2h_oen_read,
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.oen_write = &rzv2h_oen_write,
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.pin_to_oen_bit = &rzv2h_pin_to_oen_bit,
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.oen_read = &rzg2l_read_oen,
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.oen_write = &rzg2l_write_oen,
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.hw_to_bias_param = &rzv2h_hw_to_bias_param,
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.bias_param_to_hw = &rzv2h_bias_param_to_hw,
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};
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