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PCI: dwc: ep: Support BAR subrange inbound mapping via Address Match Mode iATU
Extend dw_pcie_ep_set_bar() to support inbound mappings for BAR subranges using Address Match Mode IB iATU when pci_epf_bar.num_submap is non-zero. Rename the existing BAR-match helper into dw_pcie_ep_ib_atu_bar() and introduce dw_pcie_ep_ib_atu_addr() for Address Match Mode. When num_submap is non-zero, read the assigned BAR base address and program one inbound iATU window per subrange. Validate the submap array before programming: - each subrange is aligned to pci->region_align - subranges cover the whole BAR (no gaps and no overlaps) Track Address Match Mode mappings and tear them down on clear_bar() and on set_bar() error paths to avoid leaving half-programmed state or untranslated BAR holes. Advertise this capability by extending the common feature bit initializer macro (DWC_EPC_COMMON_FEATURES). This enables multiple inbound windows within a single BAR, which is useful on platforms where usable BARs are scarce but EPFs need multiple inbound regions. Signed-off-by: Koichiro Den <den@valinux.co.jp> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Niklas Cassel <cassel@kernel.org> Link: https://patch.msgid.link/20260124145012.2794108-5-den@valinux.co.jp
This commit is contained in:
Koichiro Den
Bjorn Helgaas
parent
c0f1506f63
commit
cc839bef77
2 changed files with 209 additions and 11 deletions
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@ -100,9 +100,10 @@ static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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return 0;
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}
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static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type,
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dma_addr_t parent_bus_addr, enum pci_barno bar,
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size_t size)
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/* BAR Match Mode inbound iATU mapping */
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static int dw_pcie_ep_ib_atu_bar(struct dw_pcie_ep *ep, u8 func_no, int type,
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dma_addr_t parent_bus_addr, enum pci_barno bar,
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size_t size)
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{
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int ret;
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u32 free_win;
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@ -135,6 +136,179 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type,
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return 0;
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}
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static void dw_pcie_ep_clear_ib_maps(struct dw_pcie_ep *ep, enum pci_barno bar)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct device *dev = pci->dev;
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unsigned int i, num;
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u32 atu_index;
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u32 *indexes;
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/* Tear down the BAR Match Mode mapping, if any. */
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if (ep->bar_to_atu[bar]) {
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atu_index = ep->bar_to_atu[bar] - 1;
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dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, atu_index);
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clear_bit(atu_index, ep->ib_window_map);
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ep->bar_to_atu[bar] = 0;
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}
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/* Tear down all Address Match Mode mappings, if any. */
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indexes = ep->ib_atu_indexes[bar];
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num = ep->num_ib_atu_indexes[bar];
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ep->ib_atu_indexes[bar] = NULL;
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ep->num_ib_atu_indexes[bar] = 0;
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if (!indexes)
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return;
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for (i = 0; i < num; i++) {
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dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, indexes[i]);
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clear_bit(indexes[i], ep->ib_window_map);
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}
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devm_kfree(dev, indexes);
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}
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static u64 dw_pcie_ep_read_bar_assigned(struct dw_pcie_ep *ep, u8 func_no,
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enum pci_barno bar, int flags)
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{
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u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
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u32 lo, hi;
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u64 addr;
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lo = dw_pcie_ep_readl_dbi(ep, func_no, reg);
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if (flags & PCI_BASE_ADDRESS_SPACE)
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return lo & PCI_BASE_ADDRESS_IO_MASK;
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addr = lo & PCI_BASE_ADDRESS_MEM_MASK;
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if (!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
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return addr;
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hi = dw_pcie_ep_readl_dbi(ep, func_no, reg + 4);
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return addr | ((u64)hi << 32);
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}
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static int dw_pcie_ep_validate_submap(struct dw_pcie_ep *ep,
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const struct pci_epf_bar_submap *submap,
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unsigned int num_submap, size_t bar_size)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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u32 align = pci->region_align;
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size_t off = 0;
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unsigned int i;
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size_t size;
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if (!align || !IS_ALIGNED(bar_size, align))
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return -EINVAL;
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/*
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* The submap array order defines the BAR layout (submap[0] starts
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* at offset 0 and each entry immediately follows the previous
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* one). Here, validate that it forms a strict, gapless
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* decomposition of the BAR:
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* - each entry has a non-zero size
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* - sizes, implicit offsets and phys_addr are aligned to
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* pci->region_align
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* - each entry lies within the BAR range
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* - the entries exactly cover the whole BAR
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*
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* Note: dw_pcie_prog_inbound_atu() also checks alignment for the
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* PCI address and the target phys_addr, but validating up-front
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* avoids partially programming iATU windows in vain.
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*/
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for (i = 0; i < num_submap; i++) {
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size = submap[i].size;
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if (!size)
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return -EINVAL;
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if (!IS_ALIGNED(size, align) || !IS_ALIGNED(off, align))
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return -EINVAL;
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if (!IS_ALIGNED(submap[i].phys_addr, align))
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return -EINVAL;
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if (off > bar_size || size > bar_size - off)
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return -EINVAL;
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off += size;
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}
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if (off != bar_size)
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return -EINVAL;
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return 0;
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}
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/* Address Match Mode inbound iATU mapping */
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static int dw_pcie_ep_ib_atu_addr(struct dw_pcie_ep *ep, u8 func_no, int type,
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const struct pci_epf_bar *epf_bar)
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{
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const struct pci_epf_bar_submap *submap = epf_bar->submap;
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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enum pci_barno bar = epf_bar->barno;
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struct device *dev = pci->dev;
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u64 pci_addr, parent_bus_addr;
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u64 size, base, off = 0;
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int free_win, ret;
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unsigned int i;
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u32 *indexes;
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if (!epf_bar->num_submap || !submap || !epf_bar->size)
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return -EINVAL;
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ret = dw_pcie_ep_validate_submap(ep, submap, epf_bar->num_submap,
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epf_bar->size);
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if (ret)
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return ret;
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base = dw_pcie_ep_read_bar_assigned(ep, func_no, bar, epf_bar->flags);
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if (!base) {
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dev_err(dev,
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"BAR%u not assigned, cannot set up sub-range mappings\n",
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bar);
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return -EINVAL;
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}
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indexes = devm_kcalloc(dev, epf_bar->num_submap, sizeof(*indexes),
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GFP_KERNEL);
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if (!indexes)
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return -ENOMEM;
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ep->ib_atu_indexes[bar] = indexes;
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ep->num_ib_atu_indexes[bar] = 0;
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for (i = 0; i < epf_bar->num_submap; i++) {
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size = submap[i].size;
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parent_bus_addr = submap[i].phys_addr;
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if (off > (~0ULL) - base) {
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ret = -EINVAL;
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goto err;
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}
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pci_addr = base + off;
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off += size;
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free_win = find_first_zero_bit(ep->ib_window_map,
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pci->num_ib_windows);
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if (free_win >= pci->num_ib_windows) {
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ret = -ENOSPC;
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goto err;
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}
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ret = dw_pcie_prog_inbound_atu(pci, free_win, type,
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parent_bus_addr, pci_addr, size);
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if (ret)
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goto err;
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set_bit(free_win, ep->ib_window_map);
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indexes[i] = free_win;
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ep->num_ib_atu_indexes[bar] = i + 1;
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}
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return 0;
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err:
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dw_pcie_ep_clear_ib_maps(ep, bar);
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return ret;
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}
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static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep,
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struct dw_pcie_ob_atu_cfg *atu)
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{
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@ -165,17 +339,15 @@ static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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enum pci_barno bar = epf_bar->barno;
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u32 atu_index = ep->bar_to_atu[bar] - 1;
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if (!ep->bar_to_atu[bar])
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if (!ep->epf_bar[bar])
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return;
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__dw_pcie_ep_reset_bar(pci, func_no, bar, epf_bar->flags);
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dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, atu_index);
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clear_bit(atu_index, ep->ib_window_map);
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dw_pcie_ep_clear_ib_maps(ep, bar);
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ep->epf_bar[bar] = NULL;
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ep->bar_to_atu[bar] = 0;
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}
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static unsigned int dw_pcie_ep_get_rebar_offset(struct dw_pcie *pci,
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@ -331,11 +503,28 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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ep->epf_bar[bar]->flags != flags)
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return -EINVAL;
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/*
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* When dynamically changing a BAR, tear down any existing
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* mappings before re-programming.
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*/
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if (ep->epf_bar[bar]->num_submap || epf_bar->num_submap)
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dw_pcie_ep_clear_ib_maps(ep, bar);
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/*
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* When dynamically changing a BAR, skip writing the BAR reg, as
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* that would clear the BAR's PCI address assigned by the host.
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*/
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goto config_atu;
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} else {
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/*
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* Subrange mapping is an update-only operation. The BAR
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* must have been configured once without submaps so that
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* subsequent set_bar() calls can update inbound mappings
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* without touching the BAR register (and clobbering the
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* host-assigned address).
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*/
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if (epf_bar->num_submap)
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return -EINVAL;
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}
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bar_type = dw_pcie_ep_get_bar_type(ep, bar);
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@ -369,8 +558,12 @@ config_atu:
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else
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type = PCIE_ATU_TYPE_IO;
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ret = dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar,
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size);
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if (epf_bar->num_submap)
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ret = dw_pcie_ep_ib_atu_addr(ep, func_no, type, epf_bar);
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else
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ret = dw_pcie_ep_ib_atu_bar(ep, func_no, type,
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epf_bar->phys_addr, bar, size);
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if (ret)
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return ret;
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@ -306,7 +306,8 @@
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#define DMA_LLP_MEM_SIZE PAGE_SIZE
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/* Common struct pci_epc_feature bits among DWC EP glue drivers */
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#define DWC_EPC_COMMON_FEATURES .dynamic_inbound_mapping = true
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#define DWC_EPC_COMMON_FEATURES .dynamic_inbound_mapping = true, \
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.subrange_mapping = true
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struct dw_pcie;
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struct dw_pcie_rp;
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@ -487,6 +488,10 @@ struct dw_pcie_ep {
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phys_addr_t msi_mem_phys;
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struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS];
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/* Only for Address Match Mode inbound iATU */
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u32 *ib_atu_indexes[PCI_STD_NUM_BARS];
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unsigned int num_ib_atu_indexes[PCI_STD_NUM_BARS];
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/* MSI outbound iATU state */
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bool msi_iatu_mapped;
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u64 msi_msg_addr;
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