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Driver core changes for 7.0-rc1

Browse source 
- Bus:
   - Ensure bus->match() is consistently called with the device lock held
   - Improve type safety of bus_find_device_by_acpi_dev()
 
 - Devtmpfs:
   - Parse 'devtmpfs.mount=' boot parameter with kstrtoint() instead of
     simple_strtoul()
   - Avoid sparse warning by making devtmpfs_context_ops static
 
 - IOMMU:
   - Do not register the qcom_smmu_tbu_driver in arm_smmu_device_probe()
 
 - MAINTAINERS:
   - Add the new driver-core mailing list (driver-core@lists.linux.dev)
     to all relevant entries
   - Add missing tree location for "FIRMWARE LOADER (request_firmware)"
   - Add driver-model documentation to the "DRIVER CORE" entry
   - Add missing driver-core maintainers to the "AUXILIARY BUS" entry
 
 - Misc:
   - Change return type of attribute_container_register() to void; it has
     always been infallible
   - Do not export sysfs_change_owner(), sysfs_file_change_owner() and
     device_change_owner()
   - Move devres_for_each_res() from the public devres header to
     drivers/base/base.h
   - Do not use a static struct device for the faux bus; allocate it
     dynamically
 
 - Revocable:
   - Patches for the revocable synchronization primitive have been
     scheduled for v7.0-rc1, but have been reverted as they need some
     more refinement
 
 - Rust:
   - Device:
     - Support dev_printk on all device types, not just the core Device
       struct; remove now-redundant .as_ref() calls in dev_* print calls
 
   - Devres:
     - Introduce an internal reference count in Devres<T> to avoid a
       deadlock condition in case of (indirect) nesting
 
   - DMA:
     - Allow drivers to tune the maximum DMA segment size via
       dma_set_max_seg_size()
 
   - I/O:
     - Introduce the concept of generic I/O backends to handle different
       kinds of device shared memory through a common interface.
 
       This enables higher-level concepts such as register abstractions,
       I/O slices, and field projections to be built generically on top.
 
       In a first step, introduce the Io, IoCapable<T>, and IoKnownSize
       trait hierarchy for sharing a common interface supporting offset
       validation and bound-checking logic between I/O backends.
 
     - Refactor MMIO to use the common I/O backend infrastructure
 
   - Misc:
     - Add __rust_helper annotations to C helpers for inlining into Rust
       code
     - Use "kernel vertical" style for imports
     - Replace kernel::c_str! with C string literals
     - Update ARef imports to use sync::aref
     - Use pin_init::zeroed() for struct auxiliary_device_id and debugfs
       file_operations initialization
     - Use LKMM atomic types in debugfs doc-tests
     - Various minor comment and documentation fixes
 
   - PCI:
     - Implement PCI configuration space accessors using the common I/O
       backend infrastructure
     - Document pci::Bar device endianness assumptions
 
   - SoC:
     - Abstractions for struct soc_device and struct soc_device_attribute
     - Sample driver for soc::Device
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Merge tag 'driver-core-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/driver-core/driver-core

Pull driver core updates from Danilo Krummrich:
 "Bus:

   - Ensure bus->match() is consistently called with the device lock
     held

   - Improve type safety of bus_find_device_by_acpi_dev()

  Devtmpfs:

   - Parse 'devtmpfs.mount=' boot parameter with kstrtoint() instead of
     simple_strtoul()

   - Avoid sparse warning by making devtmpfs_context_ops static

  IOMMU:

   - Do not register the qcom_smmu_tbu_driver in arm_smmu_device_probe()

  MAINTAINERS:

   - Add the new driver-core mailing list (driver-core@lists.linux.dev)
     to all relevant entries

   - Add missing tree location for "FIRMWARE LOADER (request_firmware)"

   - Add driver-model documentation to the "DRIVER CORE" entry

   - Add missing driver-core maintainers to the "AUXILIARY BUS" entry

  Misc:

   - Change return type of attribute_container_register() to void; it
     has always been infallible

   - Do not export sysfs_change_owner(), sysfs_file_change_owner() and
     device_change_owner()

   - Move devres_for_each_res() from the public devres header to
     drivers/base/base.h

   - Do not use a static struct device for the faux bus; allocate it
     dynamically

  Revocable:

   - Patches for the revocable synchronization primitive have been
     scheduled for v7.0-rc1, but have been reverted as they need some
     more refinement

  Rust:

   - Device:
      - Support dev_printk on all device types, not just the core Device
        struct; remove now-redundant .as_ref() calls in dev_* print
        calls

   - Devres:
      - Introduce an internal reference count in Devres<T> to avoid a
        deadlock condition in case of (indirect) nesting

   - DMA:
      - Allow drivers to tune the maximum DMA segment size via
        dma_set_max_seg_size()

   - I/O:
      - Introduce the concept of generic I/O backends to handle
        different kinds of device shared memory through a common
        interface.

        This enables higher-level concepts such as register
        abstractions, I/O slices, and field projections to be built
        generically on top.

        In a first step, introduce the Io, IoCapable<T>, and IoKnownSize
        trait hierarchy for sharing a common interface supporting offset
        validation and bound-checking logic between I/O backends.

      - Refactor MMIO to use the common I/O backend infrastructure

   - Misc:
      - Add __rust_helper annotations to C helpers for inlining into
        Rust code

      - Use "kernel vertical" style for imports

      - Replace kernel::c_str! with C string literals

      - Update ARef imports to use sync::aref

      - Use pin_init::zeroed() for struct auxiliary_device_id and
        debugfs file_operations initialization

      - Use LKMM atomic types in debugfs doc-tests

      - Various minor comment and documentation fixes

   - PCI:
      - Implement PCI configuration space accessors using the common I/O
        backend infrastructure

      - Document pci::Bar device endianness assumptions

   - SoC:
      - Abstractions for struct soc_device and struct soc_device_attribute

      - Sample driver for soc::Device"

* tag 'driver-core-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/driver-core/driver-core: (79 commits)
  rust: devres: fix race condition due to nesting
  rust: dma: add missing __rust_helper annotations
  samples: rust: pci: Remove some additional `.as_ref()` for `dev_*` print
  Revert "revocable: Revocable resource management"
  Revert "revocable: Add Kunit test cases"
  Revert "selftests: revocable: Add kselftest cases"
  driver core: remove device_change_owner() export
  sysfs: remove exports of sysfs_*change_owner()
  driver core: disable revocable code from build
  revocable: Add KUnit test for concurrent access
  revocable: fix SRCU index corruption by requiring caller-provided storage
  revocable: Add KUnit test for provider lifetime races
  revocable: Fix races in revocable_alloc() using RCU
  driver core: fix inverted "locked" suffix of driver_match_device()
  rust: io: move MIN_SIZE and io_addr_assert to IoKnownSize
  rust: pci: re-export ConfigSpace
  rust: dma: allow drivers to tune max segment size
  gpu: tyr: remove redundant `.as_ref()` for `dev_*` print
  rust: auxiliary: use `pin_init::zeroed()` for device ID
  rust: debugfs: use pin_init::zeroed() for file_operations
  ...
This commit is contained in:
Linus Torvalds 2026-02-11 17:43:59 -08:00
commit c6e62d002b
68 changed files with 1612 additions and 581 deletions
Download patch file Download diff file Expand all files Collapse all files

15
MAINTAINERS
View file

@ -4191,9 +4191,12 @@ F: scripts/Makefile.autofdo
AUXILIARY BUS DRIVER
M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
M: "Rafael J. Wysocki" <rafael@kernel.org>
M: Danilo Krummrich <dakr@kernel.org>
R: Dave Ertman <david.m.ertman@intel.com>
R: Ira Weiny <ira.weiny@intel.com>
R: Leon Romanovsky <leon@kernel.org>
L: driver-core@lists.linux.dev
S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/driver-core/driver-core.git
F: Documentation/driver-api/auxiliary_bus.rst
@ -7286,7 +7289,7 @@ DEVICE I/O & IRQ [RUST]
M: Danilo Krummrich <dakr@kernel.org>
M: Alice Ryhl <aliceryhl@google.com>
M: Daniel Almeida <daniel.almeida@collabora.com>
L: rust-for-linux@vger.kernel.org
L: driver-core@lists.linux.dev
S: Supported
W: https://rust-for-linux.com
B: https://github.com/Rust-for-Linux/linux/issues
@ -7537,7 +7540,7 @@ R: Abdiel Janulgue <abdiel.janulgue@gmail.com>
R: Daniel Almeida <daniel.almeida@collabora.com>
R: Robin Murphy <robin.murphy@arm.com>
R: Andreas Hindborg <a.hindborg@kernel.org>
L: rust-for-linux@vger.kernel.org
L: driver-core@lists.linux.dev
S: Supported
W: https://rust-for-linux.com
T: git git://git.kernel.org/pub/scm/linux/kernel/git/driver-core/driver-core.git
@ -7751,9 +7754,11 @@ DRIVER CORE, KOBJECTS, DEBUGFS AND SYSFS
M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
M: "Rafael J. Wysocki" <rafael@kernel.org>
M: Danilo Krummrich <dakr@kernel.org>
L: driver-core@lists.linux.dev
S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/driver-core/driver-core.git
F: Documentation/core-api/kobject.rst
F: Documentation/driver-api/driver-model/
F: drivers/base/
F: fs/debugfs/
F: fs/sysfs/
@ -7774,10 +7779,12 @@ F: rust/kernel/devres.rs
F: rust/kernel/driver.rs
F: rust/kernel/faux.rs
F: rust/kernel/platform.rs
F: rust/kernel/soc.rs
F: samples/rust/rust_debugfs.rs
F: samples/rust/rust_debugfs_scoped.rs
F: samples/rust/rust_driver_platform.rs
F: samples/rust/rust_driver_faux.rs
F: samples/rust/rust_soc.rs
DRIVERS FOR OMAP ADAPTIVE VOLTAGE SCALING (AVS)
M: Nishanth Menon <nm@ti.com>
@ -9902,8 +9909,9 @@ FIRMWARE LOADER (request_firmware)
M: Luis Chamberlain <mcgrof@kernel.org>
M: Russ Weight <russ.weight@linux.dev>
M: Danilo Krummrich <dakr@kernel.org>
L: linux-kernel@vger.kernel.org
L: driver-core@lists.linux.dev
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/driver-core/driver-core.git
F: Documentation/firmware_class/
F: drivers/base/firmware_loader/
F: rust/kernel/firmware.rs
@ -14050,6 +14058,7 @@ F: tools/testing/selftests/kvm/x86/
KERNFS
M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
M: Tejun Heo <tj@kernel.org>
L: driver-core@lists.linux.dev
S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/driver-core/driver-core.git
F: fs/kernfs/

4
drivers/base/attribute_container.c
View file

@ -69,7 +69,7 @@ static DEFINE_MUTEX(attribute_container_mutex);
* @cont: The container to register. This must be allocated by the
* callee and should also be zeroed by it.
*/
int
void
attribute_container_register(struct attribute_container *cont)
{
INIT_LIST_HEAD(&cont->node);
@ -79,8 +79,6 @@ attribute_container_register(struct attribute_container *cont)
mutex_lock(&attribute_container_mutex);
list_add_tail(&cont->node, &attribute_container_list);
mutex_unlock(&attribute_container_mutex);
return 0;
}
EXPORT_SYMBOL_GPL(attribute_container_register);

15
drivers/base/base.h
View file

@ -179,10 +179,19 @@ void device_release_driver_internal(struct device *dev, const struct device_driv
void driver_detach(const struct device_driver *drv);
void driver_deferred_probe_del(struct device *dev);
void device_set_deferred_probe_reason(const struct device *dev, struct va_format *vaf);
static inline int driver_match_device_locked(const struct device_driver *drv,
struct device *dev)
{
device_lock_assert(dev);
return drv->bus->match ? drv->bus->match(dev, drv) : 1;
}
static inline int driver_match_device(const struct device_driver *drv,
struct device *dev)
{
return drv->bus->match ? drv->bus->match(dev, drv) : 1;
guard(device)(dev);
return driver_match_device_locked(drv, dev);
}
static inline void dev_sync_state(struct device *dev)
@ -213,6 +222,10 @@ static inline void device_set_driver(struct device *dev, const struct device_dri
WRITE_ONCE(dev->driver, (struct device_driver *)drv);
}
void devres_for_each_res(struct device *dev, dr_release_t release,
dr_match_t match, void *match_data,
void (*fn)(struct device *, void *, void *),
void *data);
int devres_release_all(struct device *dev);
void device_block_probing(void);
void device_unblock_probing(void);

1
drivers/base/core.c
View file

@ -4781,7 +4781,6 @@ out:
put_device(dev);
return error;
}
EXPORT_SYMBOL_GPL(device_change_owner);
/**
* device_shutdown - call ->shutdown() on each device to shutdown.

2
drivers/base/dd.c
View file

@ -928,7 +928,7 @@ static int __device_attach_driver(struct device_driver *drv, void *_data)
bool async_allowed;
int ret;
ret = driver_match_device(drv, dev);
ret = driver_match_device_locked(drv, dev);
if (ret == 0) {
/* no match */
return 0;

5
drivers/base/devtmpfs.c
View file

@ -56,8 +56,7 @@ static struct req {
static int __init mount_param(char *str)
{
mount_dev = simple_strtoul(str, NULL, 0);
return 1;
return kstrtoint(str, 0, &mount_dev) == 0;
}
__setup("devtmpfs.mount=", mount_param);
@ -85,7 +84,7 @@ static int devtmpfs_get_tree(struct fs_context *fc)
}
/* Ops are filled in during init depending on underlying shmem or ramfs type */
struct fs_context_operations devtmpfs_context_ops = {};
static struct fs_context_operations devtmpfs_context_ops = {};
/* Call the underlying initialization and set to our ops */
static int devtmpfs_init_fs_context(struct fs_context *fc)

18
drivers/base/faux.c
View file

@ -29,9 +29,7 @@ struct faux_object {
};
#define to_faux_object(dev) container_of_const(dev, struct faux_object, faux_dev.dev)
static struct device faux_bus_root = {
.init_name = "faux",
};
static struct device *faux_bus_root;
static int faux_match(struct device *dev, const struct device_driver *drv)
{
@ -152,7 +150,7 @@ struct faux_device *faux_device_create_with_groups(const char *name,
if (parent)
dev->parent = parent;
else
dev->parent = &faux_bus_root;
dev->parent = faux_bus_root;
dev->bus = &faux_bus_type;
dev_set_name(dev, "%s", name);
device_set_pm_not_required(dev);
@ -236,9 +234,15 @@ int __init faux_bus_init(void)
{
int ret;
ret = device_register(&faux_bus_root);
faux_bus_root = kzalloc(sizeof(*faux_bus_root), GFP_KERNEL);
if (!faux_bus_root)
return -ENOMEM;
dev_set_name(faux_bus_root, "faux");
ret = device_register(faux_bus_root);
if (ret) {
put_device(&faux_bus_root);
put_device(faux_bus_root);
return ret;
}
@ -256,6 +260,6 @@ error_driver:
bus_unregister(&faux_bus_type);
error_bus:
device_unregister(&faux_bus_root);
device_unregister(faux_bus_root);
return ret;
}

8
drivers/base/transport_class.c
View file

@ -88,17 +88,13 @@ static int anon_transport_dummy_function(struct transport_container *tc,
* events. Use prezero and then use DECLARE_ANON_TRANSPORT_CLASS() to
* initialise the anon transport class storage.
*/
int anon_transport_class_register(struct anon_transport_class *atc)
void anon_transport_class_register(struct anon_transport_class *atc)
{
int error;
atc->container.class = &atc->tclass.class;
attribute_container_set_no_classdevs(&atc->container);
error = attribute_container_register(&atc->container);
if (error)
return error;
attribute_container_register(&atc->container);
atc->tclass.setup = anon_transport_dummy_function;
atc->tclass.remove = anon_transport_dummy_function;
return 0;
}
EXPORT_SYMBOL_GPL(anon_transport_class_register);

2
drivers/gpu/drm/tyr/driver.rs
View file

@ -140,7 +140,7 @@ impl platform::Driver for TyrDriver {
// We need this to be dev_info!() because dev_dbg!() does not work at
// all in Rust for now, and we need to see whether probe succeeded.
dev_info!(pdev.as_ref(), "Tyr initialized correctly.\n");
dev_info!(pdev, "Tyr initialized correctly.\n");
Ok(driver)
}
}

6
drivers/gpu/drm/tyr/gpu.rs
View file

@ -98,7 +98,7 @@ impl GpuInfo {
};
dev_info!(
pdev.as_ref(),
pdev,
"mali-{} id 0x{:x} major 0x{:x} minor 0x{:x} status 0x{:x}",
model_name,
self.gpu_id >> 16,
@ -108,7 +108,7 @@ impl GpuInfo {
);
dev_info!(
pdev.as_ref(),
pdev,
"Features: L2:{:#x} Tiler:{:#x} Mem:{:#x} MMU:{:#x} AS:{:#x}",
self.l2_features,
self.tiler_features,
@ -118,7 +118,7 @@ impl GpuInfo {
);
dev_info!(
pdev.as_ref(),
pdev,
"shader_present=0x{:016x} l2_present=0x{:016x} tiler_present=0x{:016x}",
self.shader_present,
self.l2_present,

1
drivers/gpu/drm/tyr/regs.rs
View file

@ -11,6 +11,7 @@ use kernel::bits::bit_u32;
use kernel::device::Bound;
use kernel::device::Device;
use kernel::devres::Devres;
use kernel::io::Io;
use kernel::prelude::*;
use crate::driver::IoMem;

5
drivers/gpu/nova-core/gsp/sequencer.rs
View file

@ -6,7 +6,10 @@ use core::array;
use kernel::{
device,
io::poll::read_poll_timeout,
io::{
poll::read_poll_timeout,
Io, //
},
prelude::*,
sync::aref::ARef,
time::{

90
drivers/gpu/nova-core/regs/macros.rs
View file

@ -369,16 +369,18 @@ macro_rules! register {
/// Read the register from its address in `io`.
#[inline(always)]
pub(crate) fn read<const SIZE: usize, T>(io: &T) -> Self where
T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
pub(crate) fn read<T, I>(io: &T) -> Self where
T: ::core::ops::Deref<Target = I>,
I: ::kernel::io::IoKnownSize + ::kernel::io::IoCapable<u32>,
{
Self(io.read32($offset))
}
/// Write the value contained in `self` to the register address in `io`.
#[inline(always)]
pub(crate) fn write<const SIZE: usize, T>(self, io: &T) where
T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
pub(crate) fn write<T, I>(self, io: &T) where
T: ::core::ops::Deref<Target = I>,
I: ::kernel::io::IoKnownSize + ::kernel::io::IoCapable<u32>,
{
io.write32(self.0, $offset)
}
@ -386,11 +388,12 @@ macro_rules! register {
/// Read the register from its address in `io` and run `f` on its value to obtain a new
/// value to write back.
#[inline(always)]
pub(crate) fn update<const SIZE: usize, T, F>(
pub(crate) fn update<T, I, F>(
io: &T,
f: F,
) where
T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
T: ::core::ops::Deref<Target = I>,
I: ::kernel::io::IoKnownSize + ::kernel::io::IoCapable<u32>,
F: ::core::ops::FnOnce(Self) -> Self,
{
let reg = f(Self::read(io));
@ -408,12 +411,13 @@ macro_rules! register {
/// Read the register from `io`, using the base address provided by `base` and adding
/// the register's offset to it.
#[inline(always)]
pub(crate) fn read<const SIZE: usize, T, B>(
pub(crate) fn read<T, I, B>(
io: &T,
#[allow(unused_variables)]
base: &B,
) -> Self where
T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
T: ::core::ops::Deref<Target = I>,
I: ::kernel::io::IoKnownSize + ::kernel::io::IoCapable<u32>,
B: crate::regs::macros::RegisterBase<$base>,
{
const OFFSET: usize = $name::OFFSET;
@ -428,13 +432,14 @@ macro_rules! register {
/// Write the value contained in `self` to `io`, using the base address provided by
/// `base` and adding the register's offset to it.
#[inline(always)]
pub(crate) fn write<const SIZE: usize, T, B>(
pub(crate) fn write<T, I, B>(
self,
io: &T,
#[allow(unused_variables)]
base: &B,
) where
T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
T: ::core::ops::Deref<Target = I>,
I: ::kernel::io::IoKnownSize + ::kernel::io::IoCapable<u32>,
B: crate::regs::macros::RegisterBase<$base>,
{
const OFFSET: usize = $name::OFFSET;
@ -449,12 +454,13 @@ macro_rules! register {
/// the register's offset to it, then run `f` on its value to obtain a new value to
/// write back.
#[inline(always)]
pub(crate) fn update<const SIZE: usize, T, B, F>(
pub(crate) fn update<T, I, B, F>(
io: &T,
base: &B,
f: F,
) where
T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
T: ::core::ops::Deref<Target = I>,
I: ::kernel::io::IoKnownSize + ::kernel::io::IoCapable<u32>,
B: crate::regs::macros::RegisterBase<$base>,
F: ::core::ops::FnOnce(Self) -> Self,
{
@ -474,11 +480,12 @@ macro_rules! register {
/// Read the array register at index `idx` from its address in `io`.
#[inline(always)]
pub(crate) fn read<const SIZE: usize, T>(
pub(crate) fn read<T, I>(
io: &T,
idx: usize,
) -> Self where
T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
T: ::core::ops::Deref<Target = I>,
I: ::kernel::io::IoKnownSize + ::kernel::io::IoCapable<u32>,
{
build_assert!(idx < Self::SIZE);
@ -490,12 +497,13 @@ macro_rules! register {
/// Write the value contained in `self` to the array register with index `idx` in `io`.
#[inline(always)]
pub(crate) fn write<const SIZE: usize, T>(
pub(crate) fn write<T, I>(
self,
io: &T,
idx: usize
) where
T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
T: ::core::ops::Deref<Target = I>,
I: ::kernel::io::IoKnownSize + ::kernel::io::IoCapable<u32>,
{
build_assert!(idx < Self::SIZE);
@ -507,12 +515,13 @@ macro_rules! register {
/// Read the array register at index `idx` in `io` and run `f` on its value to obtain a
/// new value to write back.
#[inline(always)]
pub(crate) fn update<const SIZE: usize, T, F>(
pub(crate) fn update<T, I, F>(
io: &T,
idx: usize,
f: F,
) where
T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
T: ::core::ops::Deref<Target = I>,
I: ::kernel::io::IoKnownSize + ::kernel::io::IoCapable<u32>,
F: ::core::ops::FnOnce(Self) -> Self,
{
let reg = f(Self::read(io, idx));
@ -524,11 +533,12 @@ macro_rules! register {
/// The validity of `idx` is checked at run-time, and `EINVAL` is returned is the
/// access was out-of-bounds.
#[inline(always)]
pub(crate) fn try_read<const SIZE: usize, T>(
pub(crate) fn try_read<T, I>(
io: &T,
idx: usize,
) -> ::kernel::error::Result<Self> where
T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
T: ::core::ops::Deref<Target = I>,
I: ::kernel::io::IoKnownSize + ::kernel::io::IoCapable<u32>,
{
if idx < Self::SIZE {
Ok(Self::read(io, idx))
@ -542,12 +552,13 @@ macro_rules! register {
/// The validity of `idx` is checked at run-time, and `EINVAL` is returned is the
/// access was out-of-bounds.
#[inline(always)]
pub(crate) fn try_write<const SIZE: usize, T>(
pub(crate) fn try_write<T, I>(
self,
io: &T,
idx: usize,
) -> ::kernel::error::Result where
T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
T: ::core::ops::Deref<Target = I>,
I: ::kernel::io::IoKnownSize + ::kernel::io::IoCapable<u32>,
{
if idx < Self::SIZE {
Ok(self.write(io, idx))
@ -562,12 +573,13 @@ macro_rules! register {
/// The validity of `idx` is checked at run-time, and `EINVAL` is returned is the
/// access was out-of-bounds.
#[inline(always)]
pub(crate) fn try_update<const SIZE: usize, T, F>(
pub(crate) fn try_update<T, I, F>(
io: &T,
idx: usize,
f: F,
) -> ::kernel::error::Result where
T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
T: ::core::ops::Deref<Target = I>,
I: ::kernel::io::IoKnownSize + ::kernel::io::IoCapable<u32>,
F: ::core::ops::FnOnce(Self) -> Self,
{
if idx < Self::SIZE {
@ -593,13 +605,14 @@ macro_rules! register {
/// Read the array register at index `idx` from `io`, using the base address provided
/// by `base` and adding the register's offset to it.
#[inline(always)]
pub(crate) fn read<const SIZE: usize, T, B>(
pub(crate) fn read<T, I, B>(
io: &T,
#[allow(unused_variables)]
base: &B,
idx: usize,
) -> Self where
T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
T: ::core::ops::Deref<Target = I>,
I: ::kernel::io::IoKnownSize + ::kernel::io::IoCapable<u32>,
B: crate::regs::macros::RegisterBase<$base>,
{
build_assert!(idx < Self::SIZE);
@ -614,14 +627,15 @@ macro_rules! register {
/// Write the value contained in `self` to `io`, using the base address provided by
/// `base` and adding the offset of array register `idx` to it.
#[inline(always)]
pub(crate) fn write<const SIZE: usize, T, B>(
pub(crate) fn write<T, I, B>(
self,
io: &T,
#[allow(unused_variables)]
base: &B,
idx: usize
) where
T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
T: ::core::ops::Deref<Target = I>,
I: ::kernel::io::IoKnownSize + ::kernel::io::IoCapable<u32>,
B: crate::regs::macros::RegisterBase<$base>,
{
build_assert!(idx < Self::SIZE);
@ -636,13 +650,14 @@ macro_rules! register {
/// by `base` and adding the register's offset to it, then run `f` on its value to
/// obtain a new value to write back.
#[inline(always)]
pub(crate) fn update<const SIZE: usize, T, B, F>(
pub(crate) fn update<T, I, B, F>(
io: &T,
base: &B,
idx: usize,
f: F,
) where
T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
T: ::core::ops::Deref<Target = I>,
I: ::kernel::io::IoKnownSize + ::kernel::io::IoCapable<u32>,
B: crate::regs::macros::RegisterBase<$base>,
F: ::core::ops::FnOnce(Self) -> Self,
{
@ -656,12 +671,13 @@ macro_rules! register {
/// The validity of `idx` is checked at run-time, and `EINVAL` is returned is the
/// access was out-of-bounds.
#[inline(always)]
pub(crate) fn try_read<const SIZE: usize, T, B>(
pub(crate) fn try_read<T, I, B>(
io: &T,
base: &B,
idx: usize,
) -> ::kernel::error::Result<Self> where
T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
T: ::core::ops::Deref<Target = I>,
I: ::kernel::io::IoKnownSize + ::kernel::io::IoCapable<u32>,
B: crate::regs::macros::RegisterBase<$base>,
{
if idx < Self::SIZE {
@ -677,13 +693,14 @@ macro_rules! register {
/// The validity of `idx` is checked at run-time, and `EINVAL` is returned is the
/// access was out-of-bounds.
#[inline(always)]
pub(crate) fn try_write<const SIZE: usize, T, B>(
pub(crate) fn try_write<T, I, B>(
self,
io: &T,
base: &B,
idx: usize,
) -> ::kernel::error::Result where
T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
T: ::core::ops::Deref<Target = I>,
I: ::kernel::io::IoKnownSize + ::kernel::io::IoCapable<u32>,
B: crate::regs::macros::RegisterBase<$base>,
{
if idx < Self::SIZE {
@ -700,13 +717,14 @@ macro_rules! register {
/// The validity of `idx` is checked at run-time, and `EINVAL` is returned is the
/// access was out-of-bounds.
#[inline(always)]
pub(crate) fn try_update<const SIZE: usize, T, B, F>(
pub(crate) fn try_update<T, I, B, F>(
io: &T,
base: &B,
idx: usize,
f: F,
) -> ::kernel::error::Result where
T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
T: ::core::ops::Deref<Target = I>,
I: ::kernel::io::IoKnownSize + ::kernel::io::IoCapable<u32>,
B: crate::regs::macros::RegisterBase<$base>,
F: ::core::ops::FnOnce(Self) -> Self,
{

1
drivers/gpu/nova-core/vbios.rs
View file

@ -6,6 +6,7 @@ use core::convert::TryFrom;
use kernel::{
device,
io::Io,
prelude::*,
ptr::{
Alignable,

14
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
View file

@ -228,3 +228,17 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu)
return smmu;
}
int __init arm_smmu_impl_module_init(void)
{
if (IS_ENABLED(CONFIG_ARM_SMMU_QCOM))
return qcom_smmu_module_init();
return 0;
}
void __exit arm_smmu_impl_module_exit(void)
{
if (IS_ENABLED(CONFIG_ARM_SMMU_QCOM))
qcom_smmu_module_exit();
}

14
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
View file

@ -802,10 +802,6 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
{
const struct device_node *np = smmu->dev->of_node;
const struct of_device_id *match;
static u8 tbu_registered;
if (!tbu_registered++)
platform_driver_register(&qcom_smmu_tbu_driver);
#ifdef CONFIG_ACPI
if (np == NULL) {
@ -830,3 +826,13 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
return smmu;
}
int __init qcom_smmu_module_init(void)
{
return platform_driver_register(&qcom_smmu_tbu_driver);
}
void __exit qcom_smmu_module_exit(void)
{
platform_driver_unregister(&qcom_smmu_tbu_driver);
}

24
drivers/iommu/arm/arm-smmu/arm-smmu.c
View file

@ -2365,7 +2365,29 @@ static struct platform_driver arm_smmu_driver = {
.remove = arm_smmu_device_remove,
.shutdown = arm_smmu_device_shutdown,
};
module_platform_driver(arm_smmu_driver);
static int __init arm_smmu_init(void)
{
int ret;
ret = platform_driver_register(&arm_smmu_driver);
if (ret)
return ret;
ret = arm_smmu_impl_module_init();
if (ret)
platform_driver_unregister(&arm_smmu_driver);
return ret;
}
module_init(arm_smmu_init);
static void __exit arm_smmu_exit(void)
{
arm_smmu_impl_module_exit();
platform_driver_unregister(&arm_smmu_driver);
}
module_exit(arm_smmu_exit);
MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
MODULE_AUTHOR("Will Deacon <will@kernel.org>");

5
drivers/iommu/arm/arm-smmu/arm-smmu.h
View file

@ -540,6 +540,11 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu);
struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu);
struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu);
int __init arm_smmu_impl_module_init(void);
void __exit arm_smmu_impl_module_exit(void);
int __init qcom_smmu_module_init(void);
void __exit qcom_smmu_module_exit(void);
void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx);
int arm_mmu500_reset(struct arm_smmu_device *smmu);

5
drivers/pwm/pwm_th1520.rs
View file

@ -25,7 +25,10 @@ use kernel::{
clk::Clk,
device::{Bound, Core, Device},
devres,
io::mem::IoMem,
io::{
mem::IoMem,
Io, //
},
of, platform,
prelude::*,
pwm, time,

2
drivers/scsi/scsi_transport_spi.c
View file

@ -1622,7 +1622,7 @@ static __init int spi_transport_init(void)
error = transport_class_register(&spi_transport_class);
if (error)
return error;
error = anon_transport_class_register(&spi_device_class);
anon_transport_class_register(&spi_device_class);
return transport_class_register(&spi_host_class);
}

2
fs/sysfs/file.c
View file

@ -689,7 +689,6 @@ int sysfs_file_change_owner(struct kobject *kobj, const char *name, kuid_t kuid,
return error;
}
EXPORT_SYMBOL_GPL(sysfs_file_change_owner);
/**
* sysfs_change_owner - change owner of the given object.
@ -736,7 +735,6 @@ int sysfs_change_owner(struct kobject *kobj, kuid_t kuid, kgid_t kgid)
return 0;
}
EXPORT_SYMBOL_GPL(sysfs_change_owner);
/**
* sysfs_emit - scnprintf equivalent, aware of PAGE_SIZE buffer.

2
include/linux/attribute_container.h
View file

@ -36,7 +36,7 @@ attribute_container_set_no_classdevs(struct attribute_container *atc)
atc->flags |= ATTRIBUTE_CONTAINER_NO_CLASSDEVS;
}
int attribute_container_register(struct attribute_container *cont);
void attribute_container_register(struct attribute_container *cont);
int __must_check attribute_container_unregister(struct attribute_container *cont);
void attribute_container_create_device(struct device *dev,
int (*fn)(struct attribute_container *,

4
include/linux/device/bus.h
View file

@ -215,9 +215,9 @@ bus_find_next_device(const struct bus_type *bus,struct device *cur)
return bus_find_device(bus, cur, NULL, device_match_any);
}
#ifdef CONFIG_ACPI
struct acpi_device;
#ifdef CONFIG_ACPI
/**
* bus_find_device_by_acpi_dev : device iterator for locating a particular device
* matching the ACPI COMPANION device.
@ -231,7 +231,7 @@ bus_find_device_by_acpi_dev(const struct bus_type *bus, const struct acpi_device
}
#else
static inline struct device *
bus_find_device_by_acpi_dev(const struct bus_type *bus, const void *adev)
bus_find_device_by_acpi_dev(const struct bus_type *bus, const struct acpi_device *adev)
{
return NULL;
}

4
include/linux/device/devres.h
View file

@ -26,10 +26,6 @@ __devres_alloc_node(dr_release_t release, size_t size, gfp_t gfp, int nid, const
#define devres_alloc_node(release, size, gfp, nid) \
__devres_alloc_node(release, size, gfp, nid, #release)
void devres_for_each_res(struct device *dev, dr_release_t release,
dr_match_t match, void *match_data,
void (*fn)(struct device *, void *, void *),
void *data);
void devres_free(void *res);
void devres_add(struct device *dev, void *res);
void *devres_find(struct device *dev, dr_release_t release, dr_match_t match, void *match_data);

6
include/linux/transport_class.h
View file

@ -87,9 +87,9 @@ transport_unregister_device(struct device *dev)
transport_destroy_device(dev);
}
static inline int transport_container_register(struct transport_container *tc)
static inline void transport_container_register(struct transport_container *tc)
{
return attribute_container_register(&tc->ac);
attribute_container_register(&tc->ac);
}
static inline void transport_container_unregister(struct transport_container *tc)
@ -99,7 +99,7 @@ static inline void transport_container_unregister(struct transport_container *tc
}
int transport_class_register(struct transport_class *);
int anon_transport_class_register(struct anon_transport_class *);
void anon_transport_class_register(struct anon_transport_class *);
void transport_class_unregister(struct transport_class *);
void anon_transport_class_unregister(struct anon_transport_class *);

1
rust/bindings/bindings_helper.h
View file

@ -81,6 +81,7 @@
#include <linux/sched.h>
#include <linux/security.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
#include <linux/task_work.h>
#include <linux/tracepoint.h>
#include <linux/usb.h>

6
rust/helpers/auxiliary.c
View file

@ -2,12 +2,14 @@
#include <linux/auxiliary_bus.h>
void rust_helper_auxiliary_device_uninit(struct auxiliary_device *adev)
__rust_helper void
rust_helper_auxiliary_device_uninit(struct auxiliary_device *adev)
{
return auxiliary_device_uninit(adev);
}
void rust_helper_auxiliary_device_delete(struct auxiliary_device *adev)
__rust_helper void
rust_helper_auxiliary_device_delete(struct auxiliary_device *adev)
{
return auxiliary_device_delete(adev);
}

8
rust/helpers/device.c
View file

@ -2,26 +2,26 @@
#include <linux/device.h>
int rust_helper_devm_add_action(struct device *dev,
__rust_helper int rust_helper_devm_add_action(struct device *dev,
void (*action)(void *),
void *data)
{
return devm_add_action(dev, action, data);
}
int rust_helper_devm_add_action_or_reset(struct device *dev,
__rust_helper int rust_helper_devm_add_action_or_reset(struct device *dev,
void (*action)(void *),
void *data)
{
return devm_add_action_or_reset(dev, action, data);
}
void *rust_helper_dev_get_drvdata(const struct device *dev)
__rust_helper void *rust_helper_dev_get_drvdata(const struct device *dev)
{
return dev_get_drvdata(dev);
}
void rust_helper_dev_set_drvdata(struct device *dev, void *data)
__rust_helper void rust_helper_dev_set_drvdata(struct device *dev, void *data)
{
dev_set_drvdata(dev, data);
}

29
rust/helpers/dma.c
View file

@ -2,41 +2,50 @@
#include <linux/dma-mapping.h>
void *rust_helper_dma_alloc_attrs(struct device *dev, size_t size,
dma_addr_t *dma_handle, gfp_t flag,
unsigned long attrs)
__rust_helper void *rust_helper_dma_alloc_attrs(struct device *dev, size_t size,
dma_addr_t *dma_handle,
gfp_t flag, unsigned long attrs)
{
return dma_alloc_attrs(dev, size, dma_handle, flag, attrs);
}
void rust_helper_dma_free_attrs(struct device *dev, size_t size, void *cpu_addr,
dma_addr_t dma_handle, unsigned long attrs)
__rust_helper void rust_helper_dma_free_attrs(struct device *dev, size_t size,
void *cpu_addr,
dma_addr_t dma_handle,
unsigned long attrs)
{
dma_free_attrs(dev, size, cpu_addr, dma_handle, attrs);
}
int rust_helper_dma_set_mask_and_coherent(struct device *dev, u64 mask)
__rust_helper int rust_helper_dma_set_mask_and_coherent(struct device *dev,
u64 mask)
{
return dma_set_mask_and_coherent(dev, mask);
}
int rust_helper_dma_set_mask(struct device *dev, u64 mask)
__rust_helper int rust_helper_dma_set_mask(struct device *dev, u64 mask)
{
return dma_set_mask(dev, mask);
}
int rust_helper_dma_set_coherent_mask(struct device *dev, u64 mask)
__rust_helper int rust_helper_dma_set_coherent_mask(struct device *dev, u64 mask)
{
return dma_set_coherent_mask(dev, mask);
}
int rust_helper_dma_map_sgtable(struct device *dev, struct sg_table *sgt,
__rust_helper int rust_helper_dma_map_sgtable(struct device *dev, struct sg_table *sgt,
enum dma_data_direction dir, unsigned long attrs)
{
return dma_map_sgtable(dev, sgt, dir, attrs);
}
size_t rust_helper_dma_max_mapping_size(struct device *dev)
__rust_helper size_t rust_helper_dma_max_mapping_size(struct device *dev)
{
return dma_max_mapping_size(dev);
}
__rust_helper void rust_helper_dma_set_max_seg_size(struct device *dev,
unsigned int size)
{
dma_set_max_seg_size(dev, size);
}

60
rust/helpers/io.c
View file

@ -3,140 +3,144 @@
#include <linux/io.h>
#include <linux/ioport.h>
void __iomem *rust_helper_ioremap(phys_addr_t offset, size_t size)
__rust_helper void __iomem *rust_helper_ioremap(phys_addr_t offset, size_t size)
{
return ioremap(offset, size);
}
void __iomem *rust_helper_ioremap_np(phys_addr_t offset, size_t size)
__rust_helper void __iomem *rust_helper_ioremap_np(phys_addr_t offset,
size_t size)
{
return ioremap_np(offset, size);
}
void rust_helper_iounmap(void __iomem *addr)
__rust_helper void rust_helper_iounmap(void __iomem *addr)
{
iounmap(addr);
}
u8 rust_helper_readb(const void __iomem *addr)
__rust_helper u8 rust_helper_readb(const void __iomem *addr)
{
return readb(addr);
}
u16 rust_helper_readw(const void __iomem *addr)
__rust_helper u16 rust_helper_readw(const void __iomem *addr)
{
return readw(addr);
}
u32 rust_helper_readl(const void __iomem *addr)
__rust_helper u32 rust_helper_readl(const void __iomem *addr)
{
return readl(addr);
}
#ifdef CONFIG_64BIT
u64 rust_helper_readq(const void __iomem *addr)
__rust_helper u64 rust_helper_readq(const void __iomem *addr)
{
return readq(addr);
}
#endif
void rust_helper_writeb(u8 value, void __iomem *addr)
__rust_helper void rust_helper_writeb(u8 value, void __iomem *addr)
{
writeb(value, addr);
}
void rust_helper_writew(u16 value, void __iomem *addr)
__rust_helper void rust_helper_writew(u16 value, void __iomem *addr)
{
writew(value, addr);
}
void rust_helper_writel(u32 value, void __iomem *addr)
__rust_helper void rust_helper_writel(u32 value, void __iomem *addr)
{
writel(value, addr);
}
#ifdef CONFIG_64BIT
void rust_helper_writeq(u64 value, void __iomem *addr)
__rust_helper void rust_helper_writeq(u64 value, void __iomem *addr)
{
writeq(value, addr);
}
#endif
u8 rust_helper_readb_relaxed(const void __iomem *addr)
__rust_helper u8 rust_helper_readb_relaxed(const void __iomem *addr)
{
return readb_relaxed(addr);
}
u16 rust_helper_readw_relaxed(const void __iomem *addr)
__rust_helper u16 rust_helper_readw_relaxed(const void __iomem *addr)
{
return readw_relaxed(addr);
}
u32 rust_helper_readl_relaxed(const void __iomem *addr)
__rust_helper u32 rust_helper_readl_relaxed(const void __iomem *addr)
{
return readl_relaxed(addr);
}
#ifdef CONFIG_64BIT
u64 rust_helper_readq_relaxed(const void __iomem *addr)
__rust_helper u64 rust_helper_readq_relaxed(const void __iomem *addr)
{
return readq_relaxed(addr);
}
#endif
void rust_helper_writeb_relaxed(u8 value, void __iomem *addr)
__rust_helper void rust_helper_writeb_relaxed(u8 value, void __iomem *addr)
{
writeb_relaxed(value, addr);
}
void rust_helper_writew_relaxed(u16 value, void __iomem *addr)
__rust_helper void rust_helper_writew_relaxed(u16 value, void __iomem *addr)
{
writew_relaxed(value, addr);
}
void rust_helper_writel_relaxed(u32 value, void __iomem *addr)
__rust_helper void rust_helper_writel_relaxed(u32 value, void __iomem *addr)
{
writel_relaxed(value, addr);
}
#ifdef CONFIG_64BIT
void rust_helper_writeq_relaxed(u64 value, void __iomem *addr)
__rust_helper void rust_helper_writeq_relaxed(u64 value, void __iomem *addr)
{
writeq_relaxed(value, addr);
}
#endif
resource_size_t rust_helper_resource_size(struct resource *res)
__rust_helper resource_size_t rust_helper_resource_size(struct resource *res)
{
return resource_size(res);
}
struct resource *rust_helper_request_mem_region(resource_size_t start,
resource_size_t n,
__rust_helper struct resource *
rust_helper_request_mem_region(resource_size_t start, resource_size_t n,
const char *name)
{
return request_mem_region(start, n, name);
}
void rust_helper_release_mem_region(resource_size_t start, resource_size_t n)
__rust_helper void rust_helper_release_mem_region(resource_size_t start,
resource_size_t n)
{
release_mem_region(start, n);
}
struct resource *rust_helper_request_region(resource_size_t start,
resource_size_t n, const char *name)
__rust_helper struct resource *rust_helper_request_region(resource_size_t start,
resource_size_t n,
const char *name)
{
return request_region(start, n, name);
}
struct resource *rust_helper_request_muxed_region(resource_size_t start,
resource_size_t n,
__rust_helper struct resource *
rust_helper_request_muxed_region(resource_size_t start, resource_size_t n,
const char *name)
{
return request_muxed_region(start, n, name);
}
void rust_helper_release_region(resource_size_t start, resource_size_t n)
__rust_helper void rust_helper_release_region(resource_size_t start,
resource_size_t n)
{
release_region(start, n);
}

6
rust/helpers/irq.c
View file

@ -2,8 +2,10 @@
#include <linux/interrupt.h>
int rust_helper_request_irq(unsigned int irq, irq_handler_t handler,
unsigned long flags, const char *name, void *dev)
__rust_helper int rust_helper_request_irq(unsigned int irq,
irq_handler_t handler,
unsigned long flags, const char *name,
void *dev)
{
return request_irq(irq, handler, flags, name, dev);
}

17
rust/helpers/pci.c
View file

@ -2,28 +2,30 @@
#include <linux/pci.h>
u16 rust_helper_pci_dev_id(struct pci_dev *dev)
__rust_helper u16 rust_helper_pci_dev_id(struct pci_dev *dev)
{
return PCI_DEVID(dev->bus->number, dev->devfn);
}
resource_size_t rust_helper_pci_resource_start(struct pci_dev *pdev, int bar)
__rust_helper resource_size_t
rust_helper_pci_resource_start(struct pci_dev *pdev, int bar)
{
return pci_resource_start(pdev, bar);
}
resource_size_t rust_helper_pci_resource_len(struct pci_dev *pdev, int bar)
__rust_helper resource_size_t rust_helper_pci_resource_len(struct pci_dev *pdev,
int bar)
{
return pci_resource_len(pdev, bar);
}
bool rust_helper_dev_is_pci(const struct device *dev)
__rust_helper bool rust_helper_dev_is_pci(const struct device *dev)
{
return dev_is_pci(dev);
}
#ifndef CONFIG_PCI_MSI
int rust_helper_pci_alloc_irq_vectors(struct pci_dev *dev,
__rust_helper int rust_helper_pci_alloc_irq_vectors(struct pci_dev *dev,
unsigned int min_vecs,
unsigned int max_vecs,
unsigned int flags)
@ -31,12 +33,13 @@ int rust_helper_pci_alloc_irq_vectors(struct pci_dev *dev,
return pci_alloc_irq_vectors(dev, min_vecs, max_vecs, flags);
}
void rust_helper_pci_free_irq_vectors(struct pci_dev *dev)
__rust_helper void rust_helper_pci_free_irq_vectors(struct pci_dev *dev)
{
pci_free_irq_vectors(dev);
}
int rust_helper_pci_irq_vector(struct pci_dev *pdev, unsigned int nvec)
__rust_helper int rust_helper_pci_irq_vector(struct pci_dev *pdev,
unsigned int nvec)
{
return pci_irq_vector(pdev, nvec);
}

2
rust/helpers/platform.c
View file

@ -2,7 +2,7 @@
#include <linux/platform_device.h>
bool rust_helper_dev_is_platform(const struct device *dev)
__rust_helper bool rust_helper_dev_is_platform(const struct device *dev)
{
return dev_is_platform(dev);
}

2
rust/helpers/property.c
View file

@ -2,7 +2,7 @@
#include <linux/property.h>
void rust_helper_fwnode_handle_put(struct fwnode_handle *fwnode)
__rust_helper void rust_helper_fwnode_handle_put(struct fwnode_handle *fwnode)
{
fwnode_handle_put(fwnode);
}

12
rust/helpers/scatterlist.c
View file

@ -2,23 +2,25 @@
#include <linux/dma-direction.h>
dma_addr_t rust_helper_sg_dma_address(struct scatterlist *sg)
__rust_helper dma_addr_t rust_helper_sg_dma_address(struct scatterlist *sg)
{
return sg_dma_address(sg);
}
unsigned int rust_helper_sg_dma_len(struct scatterlist *sg)
__rust_helper unsigned int rust_helper_sg_dma_len(struct scatterlist *sg)
{
return sg_dma_len(sg);
}
struct scatterlist *rust_helper_sg_next(struct scatterlist *sg)
__rust_helper struct scatterlist *rust_helper_sg_next(struct scatterlist *sg)
{
return sg_next(sg);
}
void rust_helper_dma_unmap_sgtable(struct device *dev, struct sg_table *sgt,
enum dma_data_direction dir, unsigned long attrs)
__rust_helper void rust_helper_dma_unmap_sgtable(struct device *dev,
struct sg_table *sgt,
enum dma_data_direction dir,
unsigned long attrs)
{
return dma_unmap_sgtable(dev, sgt, dir, attrs);
}

30
rust/kernel/auxiliary.rs
View file

@ -5,19 +5,30 @@
//! C header: [`include/linux/auxiliary_bus.h`](srctree/include/linux/auxiliary_bus.h)
use crate::{
bindings, container_of, device,
device_id::{RawDeviceId, RawDeviceIdIndex},
bindings,
container_of,
device,
device_id::{
RawDeviceId,
RawDeviceIdIndex, //
},
devres::Devres,
driver,
error::{from_result, to_result, Result},
error::{
from_result,
to_result, //
},
prelude::*,
types::Opaque,
ThisModule,
ThisModule, //
};
use core::{
marker::PhantomData,
mem::offset_of,
ptr::{addr_of_mut, NonNull},
ptr::{
addr_of_mut,
NonNull, //
},
};
/// An adapter for the registration of auxiliary drivers.
@ -90,7 +101,7 @@ impl<T: Driver + 'static> Adapter<T> {
// SAFETY: The auxiliary bus only ever calls the probe callback with a valid pointer to a
// `struct auxiliary_device`.
//
// INVARIANT: `adev` is valid for the duration of `probe_callback()`.
// INVARIANT: `adev` is valid for the duration of `remove_callback()`.
let adev = unsafe { &*adev.cast::<Device<device::CoreInternal>>() };
// SAFETY: `remove_callback` is only ever called after a successful call to
@ -121,12 +132,7 @@ impl DeviceId {
let name = name.to_bytes_with_nul();
let modname = modname.to_bytes_with_nul();
// TODO: Replace with `bindings::auxiliary_device_id::default()` once stabilized for
// `const`.
//
// SAFETY: FFI type is valid to be zero-initialized.
let mut id: bindings::auxiliary_device_id = unsafe { core::mem::zeroed() };
let mut id: bindings::auxiliary_device_id = pin_init::zeroed();
let mut i = 0;
while i < modname.len() {
id.name[i] = modname[i];

86
rust/kernel/debugfs.rs
View file

@ -8,28 +8,52 @@
// When DebugFS is disabled, many parameters are dead. Linting for this isn't helpful.
#![cfg_attr(not(CONFIG_DEBUG_FS), allow(unused_variables))]
use crate::fmt;
use crate::prelude::*;
use crate::str::CStr;
#[cfg(CONFIG_DEBUG_FS)]
use crate::sync::Arc;
use crate::uaccess::UserSliceReader;
use core::marker::PhantomData;
use core::marker::PhantomPinned;
use crate::{
fmt,
prelude::*,
str::CStr,
uaccess::UserSliceReader, //
};
#[cfg(CONFIG_DEBUG_FS)]
use core::mem::ManuallyDrop;
use core::ops::Deref;
use core::{
marker::{
PhantomData,
PhantomPinned, //
},
ops::Deref,
};
mod traits;
pub use traits::{BinaryReader, BinaryReaderMut, BinaryWriter, Reader, Writer};
pub use traits::{
BinaryReader,
BinaryReaderMut,
BinaryWriter,
Reader,
Writer, //
};
mod callback_adapters;
use callback_adapters::{FormatAdapter, NoWriter, WritableAdapter};
use callback_adapters::{
FormatAdapter,
NoWriter,
WritableAdapter, //
};
mod file_ops;
use file_ops::{
BinaryReadFile, BinaryReadWriteFile, BinaryWriteFile, FileOps, ReadFile, ReadWriteFile,
WriteFile,
BinaryReadFile,
BinaryReadWriteFile,
BinaryWriteFile,
FileOps,
ReadFile,
ReadWriteFile,
WriteFile, //
};
#[cfg(CONFIG_DEBUG_FS)]
mod entry;
#[cfg(CONFIG_DEBUG_FS)]
@ -102,9 +126,8 @@ impl Dir {
/// # Examples
///
/// ```
/// # use kernel::c_str;
/// # use kernel::debugfs::Dir;
/// let debugfs = Dir::new(c_str!("parent"));
/// let debugfs = Dir::new(c"parent");
/// ```
pub fn new(name: &CStr) -> Self {
Dir::create(name, None)
@ -115,10 +138,9 @@ impl Dir {
/// # Examples
///
/// ```
/// # use kernel::c_str;
/// # use kernel::debugfs::Dir;
/// let parent = Dir::new(c_str!("parent"));
/// let child = parent.subdir(c_str!("child"));
/// let parent = Dir::new(c"parent");
/// let child = parent.subdir(c"child");
/// ```
pub fn subdir(&self, name: &CStr) -> Self {
Dir::create(name, Some(self))
@ -132,11 +154,10 @@ impl Dir {
/// # Examples
///
/// ```
/// # use kernel::c_str;
/// # use kernel::debugfs::Dir;
/// # use kernel::prelude::*;
/// # let dir = Dir::new(c_str!("my_debugfs_dir"));
/// let file = KBox::pin_init(dir.read_only_file(c_str!("foo"), 200), GFP_KERNEL)?;
/// # let dir = Dir::new(c"my_debugfs_dir");
/// let file = KBox::pin_init(dir.read_only_file(c"foo", 200), GFP_KERNEL)?;
/// // "my_debugfs_dir/foo" now contains the number 200.
/// // The file is removed when `file` is dropped.
/// # Ok::<(), Error>(())
@ -161,11 +182,10 @@ impl Dir {
/// # Examples
///
/// ```
/// # use kernel::c_str;
/// # use kernel::debugfs::Dir;
/// # use kernel::prelude::*;
/// # let dir = Dir::new(c_str!("my_debugfs_dir"));
/// let file = KBox::pin_init(dir.read_binary_file(c_str!("foo"), [0x1, 0x2]), GFP_KERNEL)?;
/// # let dir = Dir::new(c"my_debugfs_dir");
/// let file = KBox::pin_init(dir.read_binary_file(c"foo", [0x1, 0x2]), GFP_KERNEL)?;
/// # Ok::<(), Error>(())
/// ```
pub fn read_binary_file<'a, T, E: 'a>(
@ -187,21 +207,25 @@ impl Dir {
/// # Examples
///
/// ```
/// # use core::sync::atomic::{AtomicU32, Ordering};
/// # use kernel::c_str;
/// # use kernel::debugfs::Dir;
/// # use kernel::prelude::*;
/// # let dir = Dir::new(c_str!("foo"));
/// # use kernel::{
/// # debugfs::Dir,
/// # prelude::*,
/// # sync::atomic::{
/// # Atomic,
/// # Relaxed,
/// # },
/// # };
/// # let dir = Dir::new(c"foo");
/// let file = KBox::pin_init(
/// dir.read_callback_file(c_str!("bar"),
/// AtomicU32::new(3),
/// dir.read_callback_file(c"bar",
/// Atomic::<u32>::new(3),
/// &|val, f| {
/// let out = val.load(Ordering::Relaxed);
/// let out = val.load(Relaxed);
/// writeln!(f, "{out:#010x}")
/// }),
/// GFP_KERNEL)?;
/// // Reading "foo/bar" will show "0x00000003".
/// file.store(10, Ordering::Relaxed);
/// file.store(10, Relaxed);
/// // Reading "foo/bar" will now show "0x0000000a".
/// # Ok::<(), Error>(())
/// ```

21
rust/kernel/debugfs/callback_adapters.rs
View file

@ -4,12 +4,21 @@
//! Adapters which allow the user to supply a write or read implementation as a value rather
//! than a trait implementation. If provided, it will override the trait implementation.
use super::{Reader, Writer};
use crate::fmt;
use crate::prelude::*;
use crate::uaccess::UserSliceReader;
use core::marker::PhantomData;
use core::ops::Deref;
use super::{
Reader,
Writer, //
};
use crate::{
fmt,
prelude::*,
uaccess::UserSliceReader, //
};
use core::{
marker::PhantomData,
ops::Deref, //
};
/// # Safety
///

14
rust/kernel/debugfs/entry.rs
View file

@ -1,10 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (C) 2025 Google LLC.
use crate::debugfs::file_ops::FileOps;
use crate::ffi::c_void;
use crate::str::{CStr, CStrExt as _};
use crate::sync::Arc;
use crate::{
debugfs::file_ops::FileOps,
prelude::*,
str::{
CStr,
CStrExt as _, //
},
sync::Arc,
};
use core::marker::PhantomData;
/// Owning handle to a DebugFS entry.

43
rust/kernel/debugfs/file_ops.rs
View file

@ -1,14 +1,23 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (C) 2025 Google LLC.
use super::{BinaryReader, BinaryWriter, Reader, Writer};
use crate::debugfs::callback_adapters::Adapter;
use crate::fmt;
use crate::fs::file;
use crate::prelude::*;
use crate::seq_file::SeqFile;
use crate::seq_print;
use crate::uaccess::UserSlice;
use super::{
BinaryReader,
BinaryWriter,
Reader,
Writer, //
};
use crate::{
debugfs::callback_adapters::Adapter,
fmt,
fs::file,
prelude::*,
seq_file::SeqFile,
seq_print,
uaccess::UserSlice, //
};
use core::marker::PhantomData;
#[cfg(CONFIG_DEBUG_FS)]
@ -126,8 +135,7 @@ impl<T: Writer + Sync> ReadFile<T> for T {
llseek: Some(bindings::seq_lseek),
release: Some(bindings::single_release),
open: Some(writer_open::<Self>),
// SAFETY: `file_operations` supports zeroes in all fields.
..unsafe { core::mem::zeroed() }
..pin_init::zeroed()
};
// SAFETY: `operations` is all stock `seq_file` implementations except for `writer_open`.
// `open`'s only requirement beyond what is provided to all open functions is that the
@ -179,8 +187,7 @@ impl<T: Writer + Reader + Sync> ReadWriteFile<T> for T {
write: Some(write::<T>),
llseek: Some(bindings::seq_lseek),
release: Some(bindings::single_release),
// SAFETY: `file_operations` supports zeroes in all fields.
..unsafe { core::mem::zeroed() }
..pin_init::zeroed()
};
// SAFETY: `operations` is all stock `seq_file` implementations except for `writer_open`
// and `write`.
@ -235,8 +242,7 @@ impl<T: Reader + Sync> WriteFile<T> for T {
open: Some(write_only_open),
write: Some(write_only_write::<T>),
llseek: Some(bindings::noop_llseek),
// SAFETY: `file_operations` supports zeroes in all fields.
..unsafe { core::mem::zeroed() }
..pin_init::zeroed()
};
// SAFETY:
// * `write_only_open` populates the file private data with the inode private data
@ -288,8 +294,7 @@ impl<T: BinaryWriter + Sync> BinaryReadFile<T> for T {
read: Some(blob_read::<T>),
llseek: Some(bindings::default_llseek),
open: Some(bindings::simple_open),
// SAFETY: `file_operations` supports zeroes in all fields.
..unsafe { core::mem::zeroed() }
..pin_init::zeroed()
};
// SAFETY:
@ -343,8 +348,7 @@ impl<T: BinaryReader + Sync> BinaryWriteFile<T> for T {
write: Some(blob_write::<T>),
llseek: Some(bindings::default_llseek),
open: Some(bindings::simple_open),
// SAFETY: `file_operations` supports zeroes in all fields.
..unsafe { core::mem::zeroed() }
..pin_init::zeroed()
};
// SAFETY:
@ -369,8 +373,7 @@ impl<T: BinaryWriter + BinaryReader + Sync> BinaryReadWriteFile<T> for T {
write: Some(blob_write::<T>),
llseek: Some(bindings::default_llseek),
open: Some(bindings::simple_open),
// SAFETY: `file_operations` supports zeroes in all fields.
..unsafe { core::mem::zeroed() }
..pin_init::zeroed()
};
// SAFETY:

43
rust/kernel/debugfs/traits.rs
View file

@ -3,17 +3,38 @@
//! Traits for rendering or updating values exported to DebugFS.
use crate::alloc::Allocator;
use crate::fmt;
use crate::fs::file;
use crate::prelude::*;
use crate::sync::atomic::{Atomic, AtomicBasicOps, AtomicType, Relaxed};
use crate::sync::Arc;
use crate::sync::Mutex;
use crate::transmute::{AsBytes, FromBytes};
use crate::uaccess::{UserSliceReader, UserSliceWriter};
use core::ops::{Deref, DerefMut};
use core::str::FromStr;
use crate::{
alloc::Allocator,
fmt,
fs::file,
prelude::*,
sync::{
atomic::{
Atomic,
AtomicBasicOps,
AtomicType,
Relaxed, //
},
Arc,
Mutex, //
},
transmute::{
AsBytes,
FromBytes, //
},
uaccess::{
UserSliceReader,
UserSliceWriter, //
},
};
use core::{
ops::{
Deref,
DerefMut, //
},
str::FromStr,
};
/// A trait for types that can be written into a string.
///

32
rust/kernel/device.rs
View file

@ -5,15 +5,20 @@
//! C header: [`include/linux/device.h`](srctree/include/linux/device.h)
use crate::{
bindings, fmt,
bindings,
fmt,
prelude::*,
sync::aref::ARef,
types::{ForeignOwnable, Opaque},
types::{
ForeignOwnable,
Opaque, //
}, //
};
use core::{
any::TypeId,
marker::PhantomData,
ptr, //
};
use core::{any::TypeId, marker::PhantomData, ptr};
#[cfg(CONFIG_PRINTK)]
use crate::c_str;
pub mod property;
@ -158,7 +163,7 @@ static_assert!(core::mem::size_of::<bindings::driver_type>() >= core::mem::size_
/// `bindings::device::release` is valid to be called from any thread, hence `ARef<Device>` can be
/// dropped from any thread.
///
/// [`AlwaysRefCounted`]: kernel::types::AlwaysRefCounted
/// [`AlwaysRefCounted`]: kernel::sync::aref::AlwaysRefCounted
/// [`impl_device_context_deref`]: kernel::impl_device_context_deref
/// [`platform::Device`]: kernel::platform::Device
#[repr(transparent)]
@ -464,7 +469,7 @@ impl<Ctx: DeviceContext> Device<Ctx> {
bindings::_dev_printk(
klevel.as_ptr().cast::<crate::ffi::c_char>(),
self.as_raw(),
c_str!("%pA").as_char_ptr(),
c"%pA".as_char_ptr(),
core::ptr::from_ref(&msg).cast::<crate::ffi::c_void>(),
)
};
@ -541,7 +546,7 @@ pub trait DeviceContext: private::Sealed {}
/// [`Device<Normal>`]. It is the only [`DeviceContext`] for which it is valid to implement
/// [`AlwaysRefCounted`] for.
///
/// [`AlwaysRefCounted`]: kernel::types::AlwaysRefCounted
/// [`AlwaysRefCounted`]: kernel::sync::aref::AlwaysRefCounted
pub struct Normal;
/// The [`Core`] context is the context of a bus specific device when it appears as argument of
@ -596,6 +601,13 @@ impl DeviceContext for Core {}
impl DeviceContext for CoreInternal {}
impl DeviceContext for Normal {}
impl<Ctx: DeviceContext> AsRef<Device<Ctx>> for Device<Ctx> {
#[inline]
fn as_ref(&self) -> &Device<Ctx> {
self
}
}
/// Convert device references to bus device references.
///
/// Bus devices can implement this trait to allow abstractions to provide the bus device in
@ -715,7 +727,7 @@ macro_rules! impl_device_context_into_aref {
macro_rules! dev_printk {
($method:ident, $dev:expr, $($f:tt)*) => {
{
($dev).$method($crate::prelude::fmt!($($f)*));
$crate::device::Device::$method($dev.as_ref(), $crate::prelude::fmt!($($f)*))
}
}
}

11
rust/kernel/device/property.rs
View file

@ -14,7 +14,8 @@ use crate::{
fmt,
prelude::*,
str::{CStr, CString},
types::{ARef, Opaque},
sync::aref::ARef,
types::Opaque,
};
/// A reference-counted fwnode_handle.
@ -178,11 +179,11 @@ impl FwNode {
/// # Examples
///
/// ```
/// # use kernel::{c_str, device::{Device, property::FwNode}, str::CString};
/// # use kernel::{device::{Device, property::FwNode}, str::CString};
/// fn examples(dev: &Device) -> Result {
/// let fwnode = dev.fwnode().ok_or(ENOENT)?;
/// let b: u32 = fwnode.property_read(c_str!("some-number")).required_by(dev)?;
/// if let Some(s) = fwnode.property_read::<CString>(c_str!("some-str")).optional() {
/// let b: u32 = fwnode.property_read(c"some-number").required_by(dev)?;
/// if let Some(s) = fwnode.property_read::<CString>(c"some-str").optional() {
/// // ...
/// }
/// Ok(())
@ -359,7 +360,7 @@ impl fmt::Debug for FwNodeReferenceArgs {
}
// SAFETY: Instances of `FwNode` are always reference-counted.
unsafe impl crate::types::AlwaysRefCounted for FwNode {
unsafe impl crate::sync::aref::AlwaysRefCounted for FwNode {
fn inc_ref(&self) {
// SAFETY: The existence of a shared reference guarantees that the
// refcount is non-zero.

191
rust/kernel/devres.rs
View file

@ -8,30 +8,24 @@
use crate::{
alloc::Flags,
bindings,
device::{Bound, Device},
error::{to_result, Error, Result},
ffi::c_void,
device::{
Bound,
Device, //
},
error::to_result,
prelude::*,
revocable::{Revocable, RevocableGuard},
sync::{aref::ARef, rcu, Completion},
types::{ForeignOwnable, Opaque, ScopeGuard},
revocable::{
Revocable,
RevocableGuard, //
},
sync::{
aref::ARef,
rcu,
Arc, //
},
types::ForeignOwnable,
};
use pin_init::Wrapper;
/// [`Devres`] inner data accessed from [`Devres::callback`].
#[pin_data]
struct Inner<T: Send> {
#[pin]
data: Revocable<T>,
/// Tracks whether [`Devres::callback`] has been completed.
#[pin]
devm: Completion,
/// Tracks whether revoking [`Self::data`] has been completed.
#[pin]
revoke: Completion,
}
/// This abstraction is meant to be used by subsystems to containerize [`Device`] bound resources to
/// manage their lifetime.
///
@ -61,14 +55,17 @@ struct Inner<T: Send> {
/// devres::Devres,
/// io::{
/// Io,
/// IoRaw,
/// PhysAddr,
/// IoKnownSize,
/// Mmio,
/// MmioRaw,
/// PhysAddr, //
/// },
/// prelude::*,
/// };
/// use core::ops::Deref;
///
/// // See also [`pci::Bar`] for a real example.
/// struct IoMem<const SIZE: usize>(IoRaw<SIZE>);
/// struct IoMem<const SIZE: usize>(MmioRaw<SIZE>);
///
/// impl<const SIZE: usize> IoMem<SIZE> {
/// /// # Safety
@ -83,7 +80,7 @@ struct Inner<T: Send> {
/// return Err(ENOMEM);
/// }
///
/// Ok(IoMem(IoRaw::new(addr as usize, SIZE)?))
/// Ok(IoMem(MmioRaw::new(addr as usize, SIZE)?))
/// }
/// }
///
@ -95,28 +92,23 @@ struct Inner<T: Send> {
/// }
///
/// impl<const SIZE: usize> Deref for IoMem<SIZE> {
/// type Target = Io<SIZE>;
/// type Target = Mmio<SIZE>;
///
/// fn deref(&self) -> &Self::Target {
/// // SAFETY: The memory range stored in `self` has been properly mapped in `Self::new`.
/// unsafe { Io::from_raw(&self.0) }
/// unsafe { Mmio::from_raw(&self.0) }
/// }
/// }
/// # fn no_run(dev: &Device<Bound>) -> Result<(), Error> {
/// // SAFETY: Invalid usage for example purposes.
/// let iomem = unsafe { IoMem::<{ core::mem::size_of::<u32>() }>::new(0xBAAAAAAD)? };
/// let devres = KBox::pin_init(Devres::new(dev, iomem), GFP_KERNEL)?;
/// let devres = Devres::new(dev, iomem)?;
///
/// let res = devres.try_access().ok_or(ENXIO)?;
/// res.write8(0x42, 0x0);
/// # Ok(())
/// # }
/// ```
///
/// # Invariants
///
/// `Self::inner` is guaranteed to be initialized and is always accessed read-only.
#[pin_data(PinnedDrop)]
pub struct Devres<T: Send> {
dev: ARef<Device>,
/// Pointer to [`Self::devres_callback`].
@ -124,14 +116,7 @@ pub struct Devres<T: Send> {
/// Has to be stored, since Rust does not guarantee to always return the same address for a
/// function. However, the C API uses the address as a key.
callback: unsafe extern "C" fn(*mut c_void),
/// Contains all the fields shared with [`Self::callback`].
// TODO: Replace with `UnsafePinned`, once available.
//
// Subsequently, the `drop_in_place()` in `Devres::drop` and `Devres::new` as well as the
// explicit `Send` and `Sync' impls can be removed.
#[pin]
inner: Opaque<Inner<T>>,
_add_action: (),
data: Arc<Revocable<T>>,
}
impl<T: Send> Devres<T> {
@ -139,74 +124,48 @@ impl<T: Send> Devres<T> {
///
/// The `data` encapsulated within the returned `Devres` instance' `data` will be
/// (revoked)[`Revocable`] once the device is detached.
pub fn new<'a, E>(
dev: &'a Device<Bound>,
data: impl PinInit<T, E> + 'a,
) -> impl PinInit<Self, Error> + 'a
pub fn new<E>(dev: &Device<Bound>, data: impl PinInit<T, E>) -> Result<Self>
where
T: 'a,
Error: From<E>,
{
try_pin_init!(&this in Self {
dev: dev.into(),
callback: Self::devres_callback,
// INVARIANT: `inner` is properly initialized.
inner <- Opaque::pin_init(try_pin_init!(Inner {
devm <- Completion::new(),
revoke <- Completion::new(),
data <- Revocable::new(data),
})),
// TODO: Replace with "initializer code blocks" [1] once available.
//
// [1] https://github.com/Rust-for-Linux/pin-init/pull/69
_add_action: {
// SAFETY: `this` is a valid pointer to uninitialized memory.
let inner = unsafe { &raw mut (*this.as_ptr()).inner };
let callback = Self::devres_callback;
let data = Arc::pin_init(Revocable::new(data), GFP_KERNEL)?;
let devres_data = data.clone();
// SAFETY:
// - `dev.as_raw()` is a pointer to a valid bound device.
// - `inner` is guaranteed to be a valid for the duration of the lifetime of `Self`.
// - `devm_add_action()` is guaranteed not to call `callback` until `this` has been
// properly initialized, because we require `dev` (i.e. the *bound* device) to
// live at least as long as the returned `impl PinInit<Self, Error>`.
// - `data` is guaranteed to be a valid for the duration of the lifetime of `Self`.
// - `devm_add_action()` is guaranteed not to call `callback` for the entire lifetime of
// `dev`.
to_result(unsafe {
bindings::devm_add_action(dev.as_raw(), Some(*callback), inner.cast())
}).inspect_err(|_| {
let inner = Opaque::cast_into(inner);
// SAFETY: `inner` is a valid pointer to an `Inner<T>` and valid for both reads
// and writes.
unsafe { core::ptr::drop_in_place(inner) };
bindings::devm_add_action(
dev.as_raw(),
Some(callback),
Arc::as_ptr(&data).cast_mut().cast(),
)
})?;
},
// `devm_add_action()` was successful and has consumed the reference count.
core::mem::forget(devres_data);
Ok(Self {
dev: dev.into(),
callback,
data,
})
}
fn inner(&self) -> &Inner<T> {
// SAFETY: By the type invairants of `Self`, `inner` is properly initialized and always
// accessed read-only.
unsafe { &*self.inner.get() }
}
fn data(&self) -> &Revocable<T> {
&self.inner().data
&self.data
}
#[allow(clippy::missing_safety_doc)]
unsafe extern "C" fn devres_callback(ptr: *mut kernel::ffi::c_void) {
// SAFETY: In `Self::new` we've passed a valid pointer to `Inner` to `devm_add_action()`,
// hence `ptr` must be a valid pointer to `Inner`.
let inner = unsafe { &*ptr.cast::<Inner<T>>() };
// SAFETY: In `Self::new` we've passed a valid pointer of `Revocable<T>` to
// `devm_add_action()`, hence `ptr` must be a valid pointer to `Revocable<T>`.
let data = unsafe { Arc::from_raw(ptr.cast::<Revocable<T>>()) };
// Ensure that `inner` can't be used anymore after we signal completion of this callback.
let inner = ScopeGuard::new_with_data(inner, |inner| inner.devm.complete_all());
if !inner.data.revoke() {
// If `revoke()` returns false, it means that `Devres::drop` already started revoking
// `data` for us. Hence we have to wait until `Devres::drop` signals that it
// completed revoking `data`.
inner.revoke.wait_for_completion();
}
data.revoke();
}
fn remove_action(&self) -> bool {
@ -218,7 +177,7 @@ impl<T: Send> Devres<T> {
bindings::devm_remove_action_nowarn(
self.dev.as_raw(),
Some(self.callback),
core::ptr::from_ref(self.inner()).cast_mut().cast(),
core::ptr::from_ref(self.data()).cast_mut().cast(),
)
} == 0)
}
@ -241,8 +200,16 @@ impl<T: Send> Devres<T> {
/// # Examples
///
/// ```no_run
/// # #![cfg(CONFIG_PCI)]
/// # use kernel::{device::Core, devres::Devres, pci};
/// #![cfg(CONFIG_PCI)]
/// use kernel::{
/// device::Core,
/// devres::Devres,
/// io::{
/// Io,
/// IoKnownSize, //
/// },
/// pci, //
/// };
///
/// fn from_core(dev: &pci::Device<Core>, devres: Devres<pci::Bar<0x4>>) -> Result {
/// let bar = devres.access(dev.as_ref())?;
@ -289,31 +256,19 @@ unsafe impl<T: Send> Send for Devres<T> {}
// SAFETY: `Devres` can be shared with any task, if `T: Sync`.
unsafe impl<T: Send + Sync> Sync for Devres<T> {}
#[pinned_drop]
impl<T: Send> PinnedDrop for Devres<T> {
fn drop(self: Pin<&mut Self>) {
impl<T: Send> Drop for Devres<T> {
fn drop(&mut self) {
// SAFETY: When `drop` runs, it is guaranteed that nobody is accessing the revocable data
// anymore, hence it is safe not to wait for the grace period to finish.
if unsafe { self.data().revoke_nosync() } {
// We revoked `self.data` before the devres action did, hence try to remove it.
if !self.remove_action() {
// We could not remove the devres action, which means that it now runs concurrently,
// hence signal that `self.data` has been revoked by us successfully.
self.inner().revoke.complete_all();
// Wait for `Self::devres_callback` to be done using this object.
self.inner().devm.wait_for_completion();
if self.remove_action() {
// SAFETY: In `Self::new` we have taken an additional reference count of `self.data`
// for `devm_add_action()`. Since `remove_action()` was successful, we have to drop
// this additional reference count.
drop(unsafe { Arc::from_raw(Arc::as_ptr(&self.data)) });
}
} else {
// `Self::devres_callback` revokes `self.data` for us, hence wait for it to be done
// using this object.
self.inner().devm.wait_for_completion();
}
// INVARIANT: At this point it is guaranteed that `inner` can't be accessed any more.
//
// SAFETY: `inner` is valid for dropping.
unsafe { core::ptr::drop_in_place(self.inner.get()) };
}
}
@ -345,7 +300,13 @@ where
/// # Examples
///
/// ```no_run
/// use kernel::{device::{Bound, Device}, devres};
/// use kernel::{
/// device::{
/// Bound,
/// Device, //
/// },
/// devres, //
/// };
///
/// /// Registration of e.g. a class device, IRQ, etc.
/// struct Registration;

17
rust/kernel/dma.rs
View file

@ -85,6 +85,23 @@ pub trait Device: AsRef<device::Device<Core>> {
bindings::dma_set_mask_and_coherent(self.as_ref().as_raw(), mask.value())
})
}
/// Set the maximum size of a single DMA segment the device may request.
///
/// This method is usually called once from `probe()` as soon as the device capabilities are
/// known.
///
/// # Safety
///
/// This method must not be called concurrently with any DMA allocation or mapping primitives,
/// such as [`CoherentAllocation::alloc_attrs`].
unsafe fn dma_set_max_seg_size(&self, size: u32) {
// SAFETY:
// - By the type invariant of `device::Device`, `self.as_ref().as_raw()` is valid.
// - The safety requirement of this function guarantees that there are no concurrent calls
// to DMA allocation and mapping primitives using this parameter.
unsafe { bindings::dma_set_max_seg_size(self.as_ref().as_raw(), size) }
}
}
/// A DMA mask that holds a bitmask with the lowest `n` bits set.

12
rust/kernel/driver.rs
View file

@ -94,10 +94,14 @@
//! [`device_id`]: kernel::device_id
//! [`module_driver`]: kernel::module_driver
use crate::error::{Error, Result};
use crate::{acpi, device, of, str::CStr, try_pin_init, types::Opaque, ThisModule};
use core::pin::Pin;
use pin_init::{pin_data, pinned_drop, PinInit};
use crate::{
acpi,
device,
of,
prelude::*,
types::Opaque,
ThisModule, //
};
/// Trait describing the layout of a specific device driver.
///

13
rust/kernel/faux.rs
View file

@ -6,8 +6,17 @@
//!
//! C header: [`include/linux/device/faux.h`](srctree/include/linux/device/faux.h)
use crate::{bindings, device, error::code::*, prelude::*};
use core::ptr::{addr_of_mut, null, null_mut, NonNull};
use crate::{
bindings,
device,
prelude::*, //
};
use core::ptr::{
addr_of_mut,
null,
null_mut,
NonNull, //
};
/// The registration of a faux device.
///

491
rust/kernel/io.rs
View file

@ -32,16 +32,16 @@ pub type ResourceSize = bindings::resource_size_t;
/// By itself, the existence of an instance of this structure does not provide any guarantees that
/// the represented MMIO region does exist or is properly mapped.
///
/// Instead, the bus specific MMIO implementation must convert this raw representation into an `Io`
/// instance providing the actual memory accessors. Only by the conversion into an `Io` structure
/// any guarantees are given.
pub struct IoRaw<const SIZE: usize = 0> {
/// Instead, the bus specific MMIO implementation must convert this raw representation into an
/// `Mmio` instance providing the actual memory accessors. Only by the conversion into an `Mmio`
/// structure any guarantees are given.
pub struct MmioRaw<const SIZE: usize = 0> {
addr: usize,
maxsize: usize,
}
impl<const SIZE: usize> IoRaw<SIZE> {
/// Returns a new `IoRaw` instance on success, an error otherwise.
impl<const SIZE: usize> MmioRaw<SIZE> {
/// Returns a new `MmioRaw` instance on success, an error otherwise.
pub fn new(addr: usize, maxsize: usize) -> Result<Self> {
if maxsize < SIZE {
return Err(EINVAL);
@ -81,14 +81,16 @@ impl<const SIZE: usize> IoRaw<SIZE> {
/// ffi::c_void,
/// io::{
/// Io,
/// IoRaw,
/// IoKnownSize,
/// Mmio,
/// MmioRaw,
/// PhysAddr,
/// },
/// };
/// use core::ops::Deref;
///
/// // See also [`pci::Bar`] for a real example.
/// struct IoMem<const SIZE: usize>(IoRaw<SIZE>);
/// // See also `pci::Bar` for a real example.
/// struct IoMem<const SIZE: usize>(MmioRaw<SIZE>);
///
/// impl<const SIZE: usize> IoMem<SIZE> {
/// /// # Safety
@ -103,7 +105,7 @@ impl<const SIZE: usize> IoRaw<SIZE> {
/// return Err(ENOMEM);
/// }
///
/// Ok(IoMem(IoRaw::new(addr as usize, SIZE)?))
/// Ok(IoMem(MmioRaw::new(addr as usize, SIZE)?))
/// }
/// }
///
@ -115,11 +117,11 @@ impl<const SIZE: usize> IoRaw<SIZE> {
/// }
///
/// impl<const SIZE: usize> Deref for IoMem<SIZE> {
/// type Target = Io<SIZE>;
/// type Target = Mmio<SIZE>;
///
/// fn deref(&self) -> &Self::Target {
/// // SAFETY: The memory range stored in `self` has been properly mapped in `Self::new`.
/// unsafe { Io::from_raw(&self.0) }
/// unsafe { Mmio::from_raw(&self.0) }
/// }
/// }
///
@ -133,10 +135,67 @@ impl<const SIZE: usize> IoRaw<SIZE> {
/// # }
/// ```
#[repr(transparent)]
pub struct Io<const SIZE: usize = 0>(IoRaw<SIZE>);
pub struct Mmio<const SIZE: usize = 0>(MmioRaw<SIZE>);
/// Internal helper macros used to invoke C MMIO read functions.
///
/// This macro is intended to be used by higher-level MMIO access macros (define_read) and provides
/// a unified expansion for infallible vs. fallible read semantics. It emits a direct call into the
/// corresponding C helper and performs the required cast to the Rust return type.
///
/// # Parameters
///
/// * `$c_fn` – The C function performing the MMIO read.
/// * `$self` – The I/O backend object.
/// * `$ty` – The type of the value to be read.
/// * `$addr` – The MMIO address to read.
///
/// This macro does not perform any validation; all invariants must be upheld by the higher-level
/// abstraction invoking it.
macro_rules! call_mmio_read {
(infallible, $c_fn:ident, $self:ident, $type:ty, $addr:expr) => {
// SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
unsafe { bindings::$c_fn($addr as *const c_void) as $type }
};
(fallible, $c_fn:ident, $self:ident, $type:ty, $addr:expr) => {{
// SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
Ok(unsafe { bindings::$c_fn($addr as *const c_void) as $type })
}};
}
/// Internal helper macros used to invoke C MMIO write functions.
///
/// This macro is intended to be used by higher-level MMIO access macros (define_write) and provides
/// a unified expansion for infallible vs. fallible write semantics. It emits a direct call into the
/// corresponding C helper and performs the required cast to the Rust return type.
///
/// # Parameters
///
/// * `$c_fn` – The C function performing the MMIO write.
/// * `$self` – The I/O backend object.
/// * `$ty` – The type of the written value.
/// * `$addr` – The MMIO address to write.
/// * `$value` – The value to write.
///
/// This macro does not perform any validation; all invariants must be upheld by the higher-level
/// abstraction invoking it.
macro_rules! call_mmio_write {
(infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr) => {
// SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
unsafe { bindings::$c_fn($value, $addr as *mut c_void) }
};
(fallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr) => {{
// SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
unsafe { bindings::$c_fn($value, $addr as *mut c_void) };
Ok(())
}};
}
macro_rules! define_read {
($(#[$attr:meta])* $name:ident, $try_name:ident, $c_fn:ident -> $type_name:ty) => {
(infallible, $(#[$attr:meta])* $vis:vis $name:ident, $call_macro:ident($c_fn:ident) ->
$type_name:ty) => {
/// Read IO data from a given offset known at compile time.
///
/// Bound checks are performed on compile time, hence if the offset is not known at compile
@ -144,29 +203,34 @@ macro_rules! define_read {
$(#[$attr])*
// Always inline to optimize out error path of `io_addr_assert`.
#[inline(always)]
pub fn $name(&self, offset: usize) -> $type_name {
$vis fn $name(&self, offset: usize) -> $type_name {
let addr = self.io_addr_assert::<$type_name>(offset);
// SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
unsafe { bindings::$c_fn(addr as *const c_void) }
// SAFETY: By the type invariant `addr` is a valid address for IO operations.
$call_macro!(infallible, $c_fn, self, $type_name, addr)
}
};
(fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $call_macro:ident($c_fn:ident) ->
$type_name:ty) => {
/// Read IO data from a given offset.
///
/// Bound checks are performed on runtime, it fails if the offset (plus the type size) is
/// out of bounds.
$(#[$attr])*
pub fn $try_name(&self, offset: usize) -> Result<$type_name> {
$vis fn $try_name(&self, offset: usize) -> Result<$type_name> {
let addr = self.io_addr::<$type_name>(offset)?;
// SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
Ok(unsafe { bindings::$c_fn(addr as *const c_void) })
// SAFETY: By the type invariant `addr` is a valid address for IO operations.
$call_macro!(fallible, $c_fn, self, $type_name, addr)
}
};
}
pub(crate) use define_read;
macro_rules! define_write {
($(#[$attr:meta])* $name:ident, $try_name:ident, $c_fn:ident <- $type_name:ty) => {
(infallible, $(#[$attr:meta])* $vis:vis $name:ident, $call_macro:ident($c_fn:ident) <-
$type_name:ty) => {
/// Write IO data from a given offset known at compile time.
///
/// Bound checks are performed on compile time, hence if the offset is not known at compile
@ -174,65 +238,80 @@ macro_rules! define_write {
$(#[$attr])*
// Always inline to optimize out error path of `io_addr_assert`.
#[inline(always)]
pub fn $name(&self, value: $type_name, offset: usize) {
$vis fn $name(&self, value: $type_name, offset: usize) {
let addr = self.io_addr_assert::<$type_name>(offset);
// SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
unsafe { bindings::$c_fn(value, addr as *mut c_void) }
$call_macro!(infallible, $c_fn, self, $type_name, addr, value);
}
};
(fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $call_macro:ident($c_fn:ident) <-
$type_name:ty) => {
/// Write IO data from a given offset.
///
/// Bound checks are performed on runtime, it fails if the offset (plus the type size) is
/// out of bounds.
$(#[$attr])*
pub fn $try_name(&self, value: $type_name, offset: usize) -> Result {
$vis fn $try_name(&self, value: $type_name, offset: usize) -> Result {
let addr = self.io_addr::<$type_name>(offset)?;
// SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
unsafe { bindings::$c_fn(value, addr as *mut c_void) }
Ok(())
$call_macro!(fallible, $c_fn, self, $type_name, addr, value)
}
};
}
pub(crate) use define_write;
impl<const SIZE: usize> Io<SIZE> {
/// Converts an `IoRaw` into an `Io` instance, providing the accessors to the MMIO mapping.
///
/// # Safety
///
/// Callers must ensure that `addr` is the start of a valid I/O mapped memory region of size
/// `maxsize`.
pub unsafe fn from_raw(raw: &IoRaw<SIZE>) -> &Self {
// SAFETY: `Io` is a transparent wrapper around `IoRaw`.
unsafe { &*core::ptr::from_ref(raw).cast() }
}
/// Returns the base address of this mapping.
#[inline]
pub fn addr(&self) -> usize {
self.0.addr()
}
/// Returns the maximum size of this mapping.
#[inline]
pub fn maxsize(&self) -> usize {
self.0.maxsize()
}
#[inline]
const fn offset_valid<U>(offset: usize, size: usize) -> bool {
/// Checks whether an access of type `U` at the given `offset`
/// is valid within this region.
#[inline]
const fn offset_valid<U>(offset: usize, size: usize) -> bool {
let type_size = core::mem::size_of::<U>();
if let Some(end) = offset.checked_add(type_size) {
end <= size && offset % type_size == 0
} else {
false
}
}
}
/// Marker trait indicating that an I/O backend supports operations of a certain type.
///
/// Different I/O backends can implement this trait to expose only the operations they support.
///
/// For example, a PCI configuration space may implement `IoCapable<u8>`, `IoCapable<u16>`,
/// and `IoCapable<u32>`, but not `IoCapable<u64>`, while an MMIO region on a 64-bit
/// system might implement all four.
pub trait IoCapable<T> {}
/// Types implementing this trait (e.g. MMIO BARs or PCI config regions)
/// can perform I/O operations on regions of memory.
///
/// This is an abstract representation to be implemented by arbitrary I/O
/// backends (e.g. MMIO, PCI config space, etc.).
///
/// The [`Io`] trait provides:
/// - Base address and size information
/// - Helper methods for offset validation and address calculation
/// - Fallible (runtime checked) accessors for different data widths
///
/// Which I/O methods are available depends on which [`IoCapable<T>`] traits
/// are implemented for the type.
///
/// # Examples
///
/// For MMIO regions, all widths (u8, u16, u32, and u64 on 64-bit systems) are typically
/// supported. For PCI configuration space, u8, u16, and u32 are supported but u64 is not.
pub trait Io {
/// Returns the base address of this mapping.
fn addr(&self) -> usize;
/// Returns the maximum size of this mapping.
fn maxsize(&self) -> usize;
/// Returns the absolute I/O address for a given `offset`,
/// performing runtime bound checks.
#[inline]
fn io_addr<U>(&self, offset: usize) -> Result<usize> {
if !Self::offset_valid::<U>(offset, self.maxsize()) {
if !offset_valid::<U>(offset, self.maxsize()) {
return Err(EINVAL);
}
@ -241,51 +320,289 @@ impl<const SIZE: usize> Io<SIZE> {
self.addr().checked_add(offset).ok_or(EINVAL)
}
/// Fallible 8-bit read with runtime bounds check.
#[inline(always)]
fn try_read8(&self, _offset: usize) -> Result<u8>
where
Self: IoCapable<u8>,
{
build_error!("Backend does not support fallible 8-bit read")
}
/// Fallible 16-bit read with runtime bounds check.
#[inline(always)]
fn try_read16(&self, _offset: usize) -> Result<u16>
where
Self: IoCapable<u16>,
{
build_error!("Backend does not support fallible 16-bit read")
}
/// Fallible 32-bit read with runtime bounds check.
#[inline(always)]
fn try_read32(&self, _offset: usize) -> Result<u32>
where
Self: IoCapable<u32>,
{
build_error!("Backend does not support fallible 32-bit read")
}
/// Fallible 64-bit read with runtime bounds check.
#[inline(always)]
fn try_read64(&self, _offset: usize) -> Result<u64>
where
Self: IoCapable<u64>,
{
build_error!("Backend does not support fallible 64-bit read")
}
/// Fallible 8-bit write with runtime bounds check.
#[inline(always)]
fn try_write8(&self, _value: u8, _offset: usize) -> Result
where
Self: IoCapable<u8>,
{
build_error!("Backend does not support fallible 8-bit write")
}
/// Fallible 16-bit write with runtime bounds check.
#[inline(always)]
fn try_write16(&self, _value: u16, _offset: usize) -> Result
where
Self: IoCapable<u16>,
{
build_error!("Backend does not support fallible 16-bit write")
}
/// Fallible 32-bit write with runtime bounds check.
#[inline(always)]
fn try_write32(&self, _value: u32, _offset: usize) -> Result
where
Self: IoCapable<u32>,
{
build_error!("Backend does not support fallible 32-bit write")
}
/// Fallible 64-bit write with runtime bounds check.
#[inline(always)]
fn try_write64(&self, _value: u64, _offset: usize) -> Result
where
Self: IoCapable<u64>,
{
build_error!("Backend does not support fallible 64-bit write")
}
/// Infallible 8-bit read with compile-time bounds check.
#[inline(always)]
fn read8(&self, _offset: usize) -> u8
where
Self: IoKnownSize + IoCapable<u8>,
{
build_error!("Backend does not support infallible 8-bit read")
}
/// Infallible 16-bit read with compile-time bounds check.
#[inline(always)]
fn read16(&self, _offset: usize) -> u16
where
Self: IoKnownSize + IoCapable<u16>,
{
build_error!("Backend does not support infallible 16-bit read")
}
/// Infallible 32-bit read with compile-time bounds check.
#[inline(always)]
fn read32(&self, _offset: usize) -> u32
where
Self: IoKnownSize + IoCapable<u32>,
{
build_error!("Backend does not support infallible 32-bit read")
}
/// Infallible 64-bit read with compile-time bounds check.
#[inline(always)]
fn read64(&self, _offset: usize) -> u64
where
Self: IoKnownSize + IoCapable<u64>,
{
build_error!("Backend does not support infallible 64-bit read")
}
/// Infallible 8-bit write with compile-time bounds check.
#[inline(always)]
fn write8(&self, _value: u8, _offset: usize)
where
Self: IoKnownSize + IoCapable<u8>,
{
build_error!("Backend does not support infallible 8-bit write")
}
/// Infallible 16-bit write with compile-time bounds check.
#[inline(always)]
fn write16(&self, _value: u16, _offset: usize)
where
Self: IoKnownSize + IoCapable<u16>,
{
build_error!("Backend does not support infallible 16-bit write")
}
/// Infallible 32-bit write with compile-time bounds check.
#[inline(always)]
fn write32(&self, _value: u32, _offset: usize)
where
Self: IoKnownSize + IoCapable<u32>,
{
build_error!("Backend does not support infallible 32-bit write")
}
/// Infallible 64-bit write with compile-time bounds check.
#[inline(always)]
fn write64(&self, _value: u64, _offset: usize)
where
Self: IoKnownSize + IoCapable<u64>,
{
build_error!("Backend does not support infallible 64-bit write")
}
}
/// Trait for types with a known size at compile time.
///
/// This trait is implemented by I/O backends that have a compile-time known size,
/// enabling the use of infallible I/O accessors with compile-time bounds checking.
///
/// Types implementing this trait can use the infallible methods in [`Io`] trait
/// (e.g., `read8`, `write32`), which require `Self: IoKnownSize` bound.
pub trait IoKnownSize: Io {
/// Minimum usable size of this region.
const MIN_SIZE: usize;
/// Returns the absolute I/O address for a given `offset`,
/// performing compile-time bound checks.
// Always inline to optimize out error path of `build_assert`.
#[inline(always)]
fn io_addr_assert<U>(&self, offset: usize) -> usize {
build_assert!(Self::offset_valid::<U>(offset, SIZE));
build_assert!(offset_valid::<U>(offset, Self::MIN_SIZE));
self.addr() + offset
}
}
define_read!(read8, try_read8, readb -> u8);
define_read!(read16, try_read16, readw -> u16);
define_read!(read32, try_read32, readl -> u32);
// MMIO regions support 8, 16, and 32-bit accesses.
impl<const SIZE: usize> IoCapable<u8> for Mmio<SIZE> {}
impl<const SIZE: usize> IoCapable<u16> for Mmio<SIZE> {}
impl<const SIZE: usize> IoCapable<u32> for Mmio<SIZE> {}
// MMIO regions on 64-bit systems also support 64-bit accesses.
#[cfg(CONFIG_64BIT)]
impl<const SIZE: usize> IoCapable<u64> for Mmio<SIZE> {}
impl<const SIZE: usize> Io for Mmio<SIZE> {
/// Returns the base address of this mapping.
#[inline]
fn addr(&self) -> usize {
self.0.addr()
}
/// Returns the maximum size of this mapping.
#[inline]
fn maxsize(&self) -> usize {
self.0.maxsize()
}
define_read!(fallible, try_read8, call_mmio_read(readb) -> u8);
define_read!(fallible, try_read16, call_mmio_read(readw) -> u16);
define_read!(fallible, try_read32, call_mmio_read(readl) -> u32);
define_read!(
fallible,
#[cfg(CONFIG_64BIT)]
try_read64,
call_mmio_read(readq) -> u64
);
define_write!(fallible, try_write8, call_mmio_write(writeb) <- u8);
define_write!(fallible, try_write16, call_mmio_write(writew) <- u16);
define_write!(fallible, try_write32, call_mmio_write(writel) <- u32);
define_write!(
fallible,
#[cfg(CONFIG_64BIT)]
try_write64,
call_mmio_write(writeq) <- u64
);
define_read!(infallible, read8, call_mmio_read(readb) -> u8);
define_read!(infallible, read16, call_mmio_read(readw) -> u16);
define_read!(infallible, read32, call_mmio_read(readl) -> u32);
define_read!(
infallible,
#[cfg(CONFIG_64BIT)]
read64,
try_read64,
readq -> u64
call_mmio_read(readq) -> u64
);
define_read!(read8_relaxed, try_read8_relaxed, readb_relaxed -> u8);
define_read!(read16_relaxed, try_read16_relaxed, readw_relaxed -> u16);
define_read!(read32_relaxed, try_read32_relaxed, readl_relaxed -> u32);
define_read!(
#[cfg(CONFIG_64BIT)]
read64_relaxed,
try_read64_relaxed,
readq_relaxed -> u64
);
define_write!(write8, try_write8, writeb <- u8);
define_write!(write16, try_write16, writew <- u16);
define_write!(write32, try_write32, writel <- u32);
define_write!(infallible, write8, call_mmio_write(writeb) <- u8);
define_write!(infallible, write16, call_mmio_write(writew) <- u16);
define_write!(infallible, write32, call_mmio_write(writel) <- u32);
define_write!(
infallible,
#[cfg(CONFIG_64BIT)]
write64,
try_write64,
writeq <- u64
);
define_write!(write8_relaxed, try_write8_relaxed, writeb_relaxed <- u8);
define_write!(write16_relaxed, try_write16_relaxed, writew_relaxed <- u16);
define_write!(write32_relaxed, try_write32_relaxed, writel_relaxed <- u32);
define_write!(
#[cfg(CONFIG_64BIT)]
write64_relaxed,
try_write64_relaxed,
writeq_relaxed <- u64
call_mmio_write(writeq) <- u64
);
}
impl<const SIZE: usize> IoKnownSize for Mmio<SIZE> {
const MIN_SIZE: usize = SIZE;
}
impl<const SIZE: usize> Mmio<SIZE> {
/// Converts an `MmioRaw` into an `Mmio` instance, providing the accessors to the MMIO mapping.
///
/// # Safety
///
/// Callers must ensure that `addr` is the start of a valid I/O mapped memory region of size
/// `maxsize`.
pub unsafe fn from_raw(raw: &MmioRaw<SIZE>) -> &Self {
// SAFETY: `Mmio` is a transparent wrapper around `MmioRaw`.
unsafe { &*core::ptr::from_ref(raw).cast() }
}
define_read!(infallible, pub read8_relaxed, call_mmio_read(readb_relaxed) -> u8);
define_read!(infallible, pub read16_relaxed, call_mmio_read(readw_relaxed) -> u16);
define_read!(infallible, pub read32_relaxed, call_mmio_read(readl_relaxed) -> u32);
define_read!(
infallible,
#[cfg(CONFIG_64BIT)]
pub read64_relaxed,
call_mmio_read(readq_relaxed) -> u64
);
define_read!(fallible, pub try_read8_relaxed, call_mmio_read(readb_relaxed) -> u8);
define_read!(fallible, pub try_read16_relaxed, call_mmio_read(readw_relaxed) -> u16);
define_read!(fallible, pub try_read32_relaxed, call_mmio_read(readl_relaxed) -> u32);
define_read!(
fallible,
#[cfg(CONFIG_64BIT)]
pub try_read64_relaxed,
call_mmio_read(readq_relaxed) -> u64
);
define_write!(infallible, pub write8_relaxed, call_mmio_write(writeb_relaxed) <- u8);
define_write!(infallible, pub write16_relaxed, call_mmio_write(writew_relaxed) <- u16);
define_write!(infallible, pub write32_relaxed, call_mmio_write(writel_relaxed) <- u32);
define_write!(
infallible,
#[cfg(CONFIG_64BIT)]
pub write64_relaxed,
call_mmio_write(writeq_relaxed) <- u64
);
define_write!(fallible, pub try_write8_relaxed, call_mmio_write(writeb_relaxed) <- u8);
define_write!(fallible, pub try_write16_relaxed, call_mmio_write(writew_relaxed) <- u16);
define_write!(fallible, pub try_write32_relaxed, call_mmio_write(writel_relaxed) <- u32);
define_write!(
fallible,
#[cfg(CONFIG_64BIT)]
pub try_write64_relaxed,
call_mmio_write(writeq_relaxed) <- u64
);
}

33
rust/kernel/io/mem.rs
View file

@ -5,7 +5,6 @@
use core::ops::Deref;
use crate::{
c_str,
device::{
Bound,
Device, //
@ -17,8 +16,8 @@ use crate::{
Region,
Resource, //
},
Io,
IoRaw, //
Mmio,
MmioRaw, //
},
prelude::*,
};
@ -52,7 +51,12 @@ impl<'a> IoRequest<'a> {
/// illustration purposes.
///
/// ```no_run
/// use kernel::{bindings, c_str, platform, of, device::Core};
/// use kernel::{
/// bindings,
/// device::Core,
/// of,
/// platform,
/// };
/// struct SampleDriver;
///
/// impl platform::Driver for SampleDriver {
@ -110,7 +114,12 @@ impl<'a> IoRequest<'a> {
/// illustration purposes.
///
/// ```no_run
/// use kernel::{bindings, c_str, platform, of, device::Core};
/// use kernel::{
/// bindings,
/// device::Core,
/// of,
/// platform,
/// };
/// struct SampleDriver;
///
/// impl platform::Driver for SampleDriver {
@ -172,7 +181,7 @@ impl<const SIZE: usize> ExclusiveIoMem<SIZE> {
fn ioremap(resource: &Resource) -> Result<Self> {
let start = resource.start();
let size = resource.size();
let name = resource.name().unwrap_or(c_str!(""));
let name = resource.name().unwrap_or_default();
let region = resource
.request_region(
@ -203,7 +212,7 @@ impl<const SIZE: usize> ExclusiveIoMem<SIZE> {
}
impl<const SIZE: usize> Deref for ExclusiveIoMem<SIZE> {
type Target = Io<SIZE>;
type Target = Mmio<SIZE>;
fn deref(&self) -> &Self::Target {
&self.iomem
@ -217,10 +226,10 @@ impl<const SIZE: usize> Deref for ExclusiveIoMem<SIZE> {
///
/// # Invariants
///
/// [`IoMem`] always holds an [`IoRaw`] instance that holds a valid pointer to the
/// [`IoMem`] always holds an [`MmioRaw`] instance that holds a valid pointer to the
/// start of the I/O memory mapped region.
pub struct IoMem<const SIZE: usize = 0> {
io: IoRaw<SIZE>,
io: MmioRaw<SIZE>,
}
impl<const SIZE: usize> IoMem<SIZE> {
@ -255,7 +264,7 @@ impl<const SIZE: usize> IoMem<SIZE> {
return Err(ENOMEM);
}
let io = IoRaw::new(addr as usize, size)?;
let io = MmioRaw::new(addr as usize, size)?;
let io = IoMem { io };
Ok(io)
@ -278,10 +287,10 @@ impl<const SIZE: usize> Drop for IoMem<SIZE> {
}
impl<const SIZE: usize> Deref for IoMem<SIZE> {
type Target = Io<SIZE>;
type Target = Mmio<SIZE>;
fn deref(&self) -> &Self::Target {
// SAFETY: Safe as by the invariant of `IoMem`.
unsafe { Io::from_raw(&self.io) }
unsafe { Mmio::from_raw(&self.io) }
}
}

16
rust/kernel/io/poll.rs
View file

@ -45,12 +45,16 @@ use crate::{
/// # Examples
///
/// ```no_run
/// use kernel::io::{Io, poll::read_poll_timeout};
/// use kernel::io::{
/// Io,
/// Mmio,
/// poll::read_poll_timeout, //
/// };
/// use kernel::time::Delta;
///
/// const HW_READY: u16 = 0x01;
///
/// fn wait_for_hardware<const SIZE: usize>(io: &Io<SIZE>) -> Result {
/// fn wait_for_hardware<const SIZE: usize>(io: &Mmio<SIZE>) -> Result {
/// read_poll_timeout(
/// // The `op` closure reads the value of a specific status register.
/// || io.try_read16(0x1000),
@ -128,12 +132,16 @@ where
/// # Examples
///
/// ```no_run
/// use kernel::io::{poll::read_poll_timeout_atomic, Io};
/// use kernel::io::{
/// Io,
/// Mmio,
/// poll::read_poll_timeout_atomic, //
/// };
/// use kernel::time::Delta;
///
/// const HW_READY: u16 = 0x01;
///
/// fn wait_for_hardware<const SIZE: usize>(io: &Io<SIZE>) -> Result {
/// fn wait_for_hardware<const SIZE: usize>(io: &Mmio<SIZE>) -> Result {
/// read_poll_timeout_atomic(
/// // The `op` closure reads the value of a specific status register.
/// || io.try_read16(0x1000),

6
rust/kernel/irq/request.rs
View file

@ -139,7 +139,6 @@ impl<'a> IrqRequest<'a> {
/// [`Completion::wait_for_completion()`]: kernel::sync::Completion::wait_for_completion
///
/// ```
/// use kernel::c_str;
/// use kernel::device::{Bound, Device};
/// use kernel::irq::{self, Flags, IrqRequest, IrqReturn, Registration};
/// use kernel::prelude::*;
@ -167,7 +166,7 @@ impl<'a> IrqRequest<'a> {
/// handler: impl PinInit<Data, Error>,
/// request: IrqRequest<'_>,
/// ) -> Result<Arc<Registration<Data>>> {
/// let registration = Registration::new(request, Flags::SHARED, c_str!("my_device"), handler);
/// let registration = Registration::new(request, Flags::SHARED, c"my_device", handler);
///
/// let registration = Arc::pin_init(registration, GFP_KERNEL)?;
///
@ -340,7 +339,6 @@ impl<T: ?Sized + ThreadedHandler, A: Allocator> ThreadedHandler for Box<T, A> {
/// [`Mutex`](kernel::sync::Mutex) to provide interior mutability.
///
/// ```
/// use kernel::c_str;
/// use kernel::device::{Bound, Device};
/// use kernel::irq::{
/// self, Flags, IrqRequest, IrqReturn, ThreadedHandler, ThreadedIrqReturn,
@ -381,7 +379,7 @@ impl<T: ?Sized + ThreadedHandler, A: Allocator> ThreadedHandler for Box<T, A> {
/// request: IrqRequest<'_>,
/// ) -> Result<Arc<ThreadedRegistration<Data>>> {
/// let registration =
/// ThreadedRegistration::new(request, Flags::SHARED, c_str!("my_device"), handler);
/// ThreadedRegistration::new(request, Flags::SHARED, c"my_device", handler);
///
/// let registration = Arc::pin_init(registration, GFP_KERNEL)?;
///

2
rust/kernel/lib.rs
View file

@ -142,6 +142,8 @@ pub mod security;
pub mod seq_file;
pub mod sizes;
pub mod slice;
#[cfg(CONFIG_SOC_BUS)]
pub mod soc;
mod static_assert;
#[doc(hidden)]
pub mod std_vendor;

11
rust/kernel/pci.rs
View file

@ -40,7 +40,14 @@ pub use self::id::{
ClassMask,
Vendor, //
};
pub use self::io::Bar;
pub use self::io::{
Bar,
ConfigSpace,
ConfigSpaceKind,
ConfigSpaceSize,
Extended,
Normal, //
};
pub use self::irq::{
IrqType,
IrqTypes,
@ -351,7 +358,7 @@ impl Device {
/// // Get an instance of `Vendor`.
/// let vendor = pdev.vendor_id();
/// dev_info!(
/// pdev.as_ref(),
/// pdev,
/// "Device: Vendor={}, Device=0x{:x}\n",
/// vendor,
/// pdev.device_id()

2
rust/kernel/pci/id.rs
View file

@ -22,7 +22,7 @@ use crate::{
/// fn probe_device(pdev: &pci::Device<Core>) -> Result {
/// let pci_class = pdev.pci_class();
/// dev_info!(
/// pdev.as_ref(),
/// pdev,
/// "Detected PCI class: {}\n",
/// pci_class
/// );

210
rust/kernel/pci/io.rs
View file

@ -8,23 +8,186 @@ use crate::{
device,
devres::Devres,
io::{
define_read,
define_write,
Io,
IoRaw, //
IoCapable,
IoKnownSize,
Mmio,
MmioRaw, //
},
prelude::*,
sync::aref::ARef, //
};
use core::ops::Deref;
use core::{
marker::PhantomData,
ops::Deref, //
};
/// Represents the size of a PCI configuration space.
///
/// PCI devices can have either a *normal* (legacy) configuration space of 256 bytes,
/// or an *extended* configuration space of 4096 bytes as defined in the PCI Express
/// specification.
#[repr(usize)]
#[derive(Eq, PartialEq)]
pub enum ConfigSpaceSize {
/// 256-byte legacy PCI configuration space.
Normal = 256,
/// 4096-byte PCIe extended configuration space.
Extended = 4096,
}
impl ConfigSpaceSize {
/// Get the raw value of this enum.
#[inline(always)]
pub const fn into_raw(self) -> usize {
// CAST: PCI configuration space size is at most 4096 bytes, so the value always fits
// within `usize` without truncation or sign change.
self as usize
}
}
/// Marker type for normal (256-byte) PCI configuration space.
pub struct Normal;
/// Marker type for extended (4096-byte) PCIe configuration space.
pub struct Extended;
/// Trait for PCI configuration space size markers.
///
/// This trait is implemented by [`Normal`] and [`Extended`] to provide
/// compile-time knowledge of the configuration space size.
pub trait ConfigSpaceKind {
/// The size of this configuration space in bytes.
const SIZE: usize;
}
impl ConfigSpaceKind for Normal {
const SIZE: usize = 256;
}
impl ConfigSpaceKind for Extended {
const SIZE: usize = 4096;
}
/// The PCI configuration space of a device.
///
/// Provides typed read and write accessors for configuration registers
/// using the standard `pci_read_config_*` and `pci_write_config_*` helpers.
///
/// The generic parameter `S` indicates the maximum size of the configuration space.
/// Use [`Normal`] for 256-byte legacy configuration space or [`Extended`] for
/// 4096-byte PCIe extended configuration space (default).
pub struct ConfigSpace<'a, S: ConfigSpaceKind = Extended> {
pub(crate) pdev: &'a Device<device::Bound>,
_marker: PhantomData<S>,
}
/// Internal helper macros used to invoke C PCI configuration space read functions.
///
/// This macro is intended to be used by higher-level PCI configuration space access macros
/// (define_read) and provides a unified expansion for infallible vs. fallible read semantics. It
/// emits a direct call into the corresponding C helper and performs the required cast to the Rust
/// return type.
///
/// # Parameters
///
/// * `$c_fn` – The C function performing the PCI configuration space write.
/// * `$self` – The I/O backend object.
/// * `$ty` – The type of the value to read.
/// * `$addr` – The PCI configuration space offset to read.
///
/// This macro does not perform any validation; all invariants must be upheld by the higher-level
/// abstraction invoking it.
macro_rules! call_config_read {
(infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr) => {{
let mut val: $ty = 0;
// SAFETY: By the type invariant `$self.pdev` is a valid address.
// CAST: The offset is cast to `i32` because the C functions expect a 32-bit signed offset
// parameter. PCI configuration space size is at most 4096 bytes, so the value always fits
// within `i32` without truncation or sign change.
// Return value from C function is ignored in infallible accessors.
let _ret = unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr as i32, &mut val) };
val
}};
}
/// Internal helper macros used to invoke C PCI configuration space write functions.
///
/// This macro is intended to be used by higher-level PCI configuration space access macros
/// (define_write) and provides a unified expansion for infallible vs. fallible read semantics. It
/// emits a direct call into the corresponding C helper and performs the required cast to the Rust
/// return type.
///
/// # Parameters
///
/// * `$c_fn` – The C function performing the PCI configuration space write.
/// * `$self` – The I/O backend object.
/// * `$ty` – The type of the written value.
/// * `$addr` – The configuration space offset to write.
/// * `$value` – The value to write.
///
/// This macro does not perform any validation; all invariants must be upheld by the higher-level
/// abstraction invoking it.
macro_rules! call_config_write {
(infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr) => {
// SAFETY: By the type invariant `$self.pdev` is a valid address.
// CAST: The offset is cast to `i32` because the C functions expect a 32-bit signed offset
// parameter. PCI configuration space size is at most 4096 bytes, so the value always fits
// within `i32` without truncation or sign change.
// Return value from C function is ignored in infallible accessors.
let _ret = unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr as i32, $value) };
};
}
// PCI configuration space supports 8, 16, and 32-bit accesses.
impl<'a, S: ConfigSpaceKind> IoCapable<u8> for ConfigSpace<'a, S> {}
impl<'a, S: ConfigSpaceKind> IoCapable<u16> for ConfigSpace<'a, S> {}
impl<'a, S: ConfigSpaceKind> IoCapable<u32> for ConfigSpace<'a, S> {}
impl<'a, S: ConfigSpaceKind> Io for ConfigSpace<'a, S> {
/// Returns the base address of the I/O region. It is always 0 for configuration space.
#[inline]
fn addr(&self) -> usize {
0
}
/// Returns the maximum size of the configuration space.
#[inline]
fn maxsize(&self) -> usize {
self.pdev.cfg_size().into_raw()
}
// PCI configuration space does not support fallible operations.
// The default implementations from the Io trait are not used.
define_read!(infallible, read8, call_config_read(pci_read_config_byte) -> u8);
define_read!(infallible, read16, call_config_read(pci_read_config_word) -> u16);
define_read!(infallible, read32, call_config_read(pci_read_config_dword) -> u32);
define_write!(infallible, write8, call_config_write(pci_write_config_byte) <- u8);
define_write!(infallible, write16, call_config_write(pci_write_config_word) <- u16);
define_write!(infallible, write32, call_config_write(pci_write_config_dword) <- u32);
}
impl<'a, S: ConfigSpaceKind> IoKnownSize for ConfigSpace<'a, S> {
const MIN_SIZE: usize = S::SIZE;
}
/// A PCI BAR to perform I/O-Operations on.
///
/// I/O backend assumes that the device is little-endian and will automatically
/// convert from little-endian to CPU endianness.
///
/// # Invariants
///
/// `Bar` always holds an `IoRaw` instance that holds a valid pointer to the start of the I/O
/// memory mapped PCI BAR and its size.
pub struct Bar<const SIZE: usize = 0> {
pdev: ARef<Device>,
io: IoRaw<SIZE>,
io: MmioRaw<SIZE>,
num: i32,
}
@ -60,7 +223,7 @@ impl<const SIZE: usize> Bar<SIZE> {
return Err(ENOMEM);
}
let io = match IoRaw::new(ioptr, len as usize) {
let io = match MmioRaw::new(ioptr, len as usize) {
Ok(io) => io,
Err(err) => {
// SAFETY:
@ -114,11 +277,11 @@ impl<const SIZE: usize> Drop for Bar<SIZE> {
}
impl<const SIZE: usize> Deref for Bar<SIZE> {
type Target = Io<SIZE>;
type Target = Mmio<SIZE>;
fn deref(&self) -> &Self::Target {
// SAFETY: By the type invariant of `Self`, the MMIO range in `self.io` is properly mapped.
unsafe { Io::from_raw(&self.io) }
unsafe { Mmio::from_raw(&self.io) }
}
}
@ -141,4 +304,39 @@ impl Device<device::Bound> {
) -> impl PinInit<Devres<Bar>, Error> + 'a {
self.iomap_region_sized::<0>(bar, name)
}
/// Returns the size of configuration space.
pub fn cfg_size(&self) -> ConfigSpaceSize {
// SAFETY: `self.as_raw` is a valid pointer to a `struct pci_dev`.
let size = unsafe { (*self.as_raw()).cfg_size };
match size {
256 => ConfigSpaceSize::Normal,
4096 => ConfigSpaceSize::Extended,
_ => {
// PANIC: The PCI subsystem only ever reports the configuration space size as either
// `ConfigSpaceSize::Normal` or `ConfigSpaceSize::Extended`.
unreachable!();
}
}
}
/// Return an initialized normal (256-byte) config space object.
pub fn config_space<'a>(&'a self) -> ConfigSpace<'a, Normal> {
ConfigSpace {
pdev: self,
_marker: PhantomData,
}
}
/// Return an initialized extended (4096-byte) config space object.
pub fn config_space_extended<'a>(&'a self) -> Result<ConfigSpace<'a, Extended>> {
if self.cfg_size() != ConfigSpaceSize::Extended {
return Err(EINVAL);
}
Ok(ConfigSpace {
pdev: self,
_marker: PhantomData,
})
}
}

46
rust/kernel/platform.rs
View file

@ -5,22 +5,39 @@
//! C header: [`include/linux/platform_device.h`](srctree/include/linux/platform_device.h)
use crate::{
acpi, bindings, container_of,
device::{self, Bound},
acpi,
bindings,
container_of,
device::{
self,
Bound, //
},
driver,
error::{from_result, to_result, Result},
io::{mem::IoRequest, Resource},
irq::{self, IrqRequest},
error::{
from_result,
to_result, //
},
io::{
mem::IoRequest,
Resource, //
},
irq::{
self,
IrqRequest, //
},
of,
prelude::*,
types::Opaque,
ThisModule,
ThisModule, //
};
use core::{
marker::PhantomData,
mem::offset_of,
ptr::{addr_of_mut, NonNull},
ptr::{
addr_of_mut,
NonNull, //
},
};
/// An adapter for the registration of platform drivers.
@ -95,7 +112,7 @@ impl<T: Driver + 'static> Adapter<T> {
// SAFETY: The platform bus only ever calls the remove callback with a valid pointer to a
// `struct platform_device`.
//
// INVARIANT: `pdev` is valid for the duration of `probe_callback()`.
// INVARIANT: `pdev` is valid for the duration of `remove_callback()`.
let pdev = unsafe { &*pdev.cast::<Device<device::CoreInternal>>() };
// SAFETY: `remove_callback` is only ever called after a successful call to
@ -146,8 +163,13 @@ macro_rules! module_platform_driver {
/// # Examples
///
///```
/// # use kernel::{acpi, bindings, c_str, device::Core, of, platform};
///
/// # use kernel::{
/// # acpi,
/// # bindings,
/// # device::Core,
/// # of,
/// # platform,
/// # };
/// struct MyDriver;
///
/// kernel::of_device_table!(
@ -155,7 +177,7 @@ macro_rules! module_platform_driver {
/// MODULE_OF_TABLE,
/// <MyDriver as platform::Driver>::IdInfo,
/// [
/// (of::DeviceId::new(c_str!("test,device")), ())
/// (of::DeviceId::new(c"test,device"), ())
/// ]
/// );
///
@ -164,7 +186,7 @@ macro_rules! module_platform_driver {
/// MODULE_ACPI_TABLE,
/// <MyDriver as platform::Driver>::IdInfo,
/// [
/// (acpi::DeviceId::new(c_str!("LNUXBEEF")), ())
/// (acpi::DeviceId::new(c"LNUXBEEF"), ())
/// ]
/// );
///

3
rust/kernel/scatterlist.rs
View file

@ -38,7 +38,8 @@ use crate::{
io::ResourceSize,
page,
prelude::*,
types::{ARef, Opaque},
sync::aref::ARef,
types::Opaque,
};
use core::{ops::Deref, ptr::NonNull};

135
rust/kernel/soc.rs Normal file
View file

@ -0,0 +1,135 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (C) 2025 Google LLC.
//! SoC Driver Abstraction.
//!
//! C header: [`include/linux/sys_soc.h`](srctree/include/linux/sys_soc.h)
use crate::{
bindings,
error,
prelude::*,
str::CString,
types::Opaque, //
};
use core::ptr::NonNull;
/// Attributes for a SoC device.
///
/// These are both exported to userspace under /sys/devices/socX and provided to other drivers to
/// match against via `soc_device_match` (not yet available in Rust) to enable quirks or
/// device-specific support where necessary.
///
/// All fields are freeform - they have no specific formatting, just defined meanings.
/// For example, the [`machine`](`Attributes::machine`) field could be "DB8500" or
/// "Qualcomm Technologies, Inc. SM8560 HDK", but regardless it should identify a board or product.
pub struct Attributes {
/// Should generally be a board ID or product ID. Examples
/// include DB8500 (ST-Ericsson) or "Qualcomm Technologies, inc. SM8560 HDK".
///
/// If this field is not populated, the SoC infrastructure will try to populate it from
/// `/model` in the device tree.
pub machine: Option<CString>,
/// The broader class this SoC belongs to. Examples include ux500
/// (for DB8500) or Snapdragon (for SM8650).
///
/// On chips with ARM firmware supporting SMCCC v1.2+, this may be a JEDEC JEP106 manufacturer
/// identification.
pub family: Option<CString>,
/// The manufacturing revision of the part. Frequently this is MAJOR.MINOR, but not always.
pub revision: Option<CString>,
/// Serial Number - uniquely identifies a specific SoC. If present, should be unique (buying a
/// replacement part should change it if present). This field cannot be matched on and is
/// solely present to export through /sys.
pub serial_number: Option<CString>,
/// SoC ID - identifies a specific SoC kind in question, sometimes more specifically than
/// `machine` if the same SoC is used in multiple products. Some devices use this to specify a
/// SoC name, e.g. "I.MX??", and others just print an ID number (e.g. Tegra and Qualcomm).
///
/// On chips with ARM firmware supporting SMCCC v1.2+, this may be a JEDEC JEP106 manufacturer
/// identification (the family value) followed by a colon and then a 4-digit ID value.
pub soc_id: Option<CString>,
}
struct BuiltAttributes {
// While `inner` has pointers to `_backing`, it is to the interior of the `CStrings`, not
// `backing` itself, so it does not need to be pinned.
_backing: Attributes,
// `Opaque` makes us `!Unpin`, as the registration holds a pointer to `inner` when used.
inner: Opaque<bindings::soc_device_attribute>,
}
fn cstring_to_c(mcs: &Option<CString>) -> *const kernel::ffi::c_char {
mcs.as_ref()
.map(|cs| cs.as_char_ptr())
.unwrap_or(core::ptr::null())
}
impl BuiltAttributes {
fn as_mut_ptr(&self) -> *mut bindings::soc_device_attribute {
self.inner.get()
}
}
impl Attributes {
fn build(self) -> BuiltAttributes {
BuiltAttributes {
inner: Opaque::new(bindings::soc_device_attribute {
machine: cstring_to_c(&self.machine),
family: cstring_to_c(&self.family),
revision: cstring_to_c(&self.revision),
serial_number: cstring_to_c(&self.serial_number),
soc_id: cstring_to_c(&self.soc_id),
data: core::ptr::null(),
custom_attr_group: core::ptr::null(),
}),
_backing: self,
}
}
}
#[pin_data(PinnedDrop)]
/// Registration handle for your soc_dev. If you let it go out of scope, your soc_dev will be
/// unregistered.
pub struct Registration {
#[pin]
attr: BuiltAttributes,
soc_dev: NonNull<bindings::soc_device>,
}
// SAFETY: We provide no operations through `&Registration`.
unsafe impl Sync for Registration {}
// SAFETY: All pointers are normal allocations, not thread-specific.
unsafe impl Send for Registration {}
#[pinned_drop]
impl PinnedDrop for Registration {
fn drop(self: Pin<&mut Self>) {
// SAFETY: Device always contains a live pointer to a soc_device that can be unregistered
unsafe { bindings::soc_device_unregister(self.soc_dev.as_ptr()) }
}
}
impl Registration {
/// Register a new SoC device
pub fn new(attr: Attributes) -> impl PinInit<Self, Error> {
try_pin_init!(Self {
attr: attr.build(),
soc_dev: {
// SAFETY:
// * The struct provided through attr is backed by pinned data next to it,
// so as long as attr lives, the strings pointed to by the struct will too.
// * `attr` is pinned, so the pinned data won't move.
// * If it returns a device, and so others may try to read this data, by
// caller invariant, `attr` won't be released until the device is.
let raw_soc = error::from_err_ptr(unsafe {
bindings::soc_device_register(attr.as_mut_ptr())
})?;
NonNull::new(raw_soc).ok_or(EINVAL)?
},
}? Error)
}
}

11
samples/rust/Kconfig
View file

@ -161,6 +161,17 @@ config SAMPLE_RUST_DRIVER_AUXILIARY
If unsure, say N.
config SAMPLE_RUST_SOC
tristate "SoC Driver"
select SOC_BUS
help
This option builds the Rust SoC driver sample.
To compile this as a module, choose M here:
the module will be called rust_soc.
If unsure, say N.
config SAMPLE_RUST_HOSTPROGS
bool "Host programs"
help

1
samples/rust/Makefile
View file

@ -15,6 +15,7 @@ obj-$(CONFIG_SAMPLE_RUST_DRIVER_USB) += rust_driver_usb.o
obj-$(CONFIG_SAMPLE_RUST_DRIVER_FAUX) += rust_driver_faux.o
obj-$(CONFIG_SAMPLE_RUST_DRIVER_AUXILIARY) += rust_driver_auxiliary.o
obj-$(CONFIG_SAMPLE_RUST_CONFIGFS) += rust_configfs.o
obj-$(CONFIG_SAMPLE_RUST_SOC) += rust_soc.o
rust_print-y := rust_print_main.o rust_print_events.o

46
samples/rust/rust_debugfs.rs
View file

@ -32,14 +32,28 @@
//! ```
use core::str::FromStr;
use kernel::c_str;
use kernel::debugfs::{Dir, File};
use kernel::new_mutex;
use kernel::prelude::*;
use kernel::sizes::*;
use kernel::sync::atomic::{Atomic, Relaxed};
use kernel::sync::Mutex;
use kernel::{acpi, device::Core, of, platform, str::CString, types::ARef};
use kernel::{
acpi,
debugfs::{
Dir,
File, //
},
device::Core,
new_mutex,
of,
platform,
prelude::*,
sizes::*,
str::CString,
sync::{
aref::ARef,
atomic::{
Atomic,
Relaxed, //
},
Mutex,
}, //
};
kernel::module_platform_driver! {
type: RustDebugFs,
@ -98,7 +112,7 @@ kernel::acpi_device_table!(
ACPI_TABLE,
MODULE_ACPI_TABLE,
<RustDebugFs as platform::Driver>::IdInfo,
[(acpi::DeviceId::new(c_str!("LNUXBEEF")), ())]
[(acpi::DeviceId::new(c"LNUXBEEF"), ())]
);
impl platform::Driver for RustDebugFs {
@ -125,34 +139,34 @@ impl platform::Driver for RustDebugFs {
impl RustDebugFs {
fn build_counter(dir: &Dir) -> impl PinInit<File<Atomic<usize>>> + '_ {
dir.read_write_file(c_str!("counter"), Atomic::<usize>::new(0))
dir.read_write_file(c"counter", Atomic::<usize>::new(0))
}
fn build_inner(dir: &Dir) -> impl PinInit<File<Mutex<Inner>>> + '_ {
dir.read_write_file(c_str!("pair"), new_mutex!(Inner { x: 3, y: 10 }))
dir.read_write_file(c"pair", new_mutex!(Inner { x: 3, y: 10 }))
}
fn new(pdev: &platform::Device<Core>) -> impl PinInit<Self, Error> + '_ {
let debugfs = Dir::new(c_str!("sample_debugfs"));
let debugfs = Dir::new(c"sample_debugfs");
let dev = pdev.as_ref();
try_pin_init! {
Self {
_compatible <- debugfs.read_only_file(
c_str!("compatible"),
c"compatible",
dev.fwnode()
.ok_or(ENOENT)?
.property_read::<CString>(c_str!("compatible"))
.property_read::<CString>(c"compatible")
.required_by(dev)?,
),
counter <- Self::build_counter(&debugfs),
inner <- Self::build_inner(&debugfs),
array_blob <- debugfs.read_write_binary_file(
c_str!("array_blob"),
c"array_blob",
new_mutex!([0x62, 0x6c, 0x6f, 0x62]),
),
vector_blob <- debugfs.read_write_binary_file(
c_str!("vector_blob"),
c"vector_blob",
new_mutex!(kernel::kvec!(0x42; SZ_4K)?),
),
_debugfs: debugfs,

38
samples/rust/rust_debugfs_scoped.rs
View file

@ -6,12 +6,20 @@
//! `Scope::dir` to create a variety of files without the need to separately
//! track them all.
use kernel::debugfs::{Dir, Scope};
use kernel::prelude::*;
use kernel::sizes::*;
use kernel::sync::atomic::Atomic;
use kernel::sync::Mutex;
use kernel::{c_str, new_mutex, str::CString};
use kernel::{
debugfs::{
Dir,
Scope, //
},
new_mutex,
prelude::*,
sizes::*,
str::CString,
sync::{
atomic::Atomic,
Mutex, //
},
};
module! {
type: RustScopedDebugFs,
@ -80,7 +88,7 @@ fn create_file_write(
};
dir.read_write_file(&name, val);
}
dir.read_write_binary_file(c_str!("blob"), &dev_data.blob);
dir.read_write_binary_file(c"blob", &dev_data.blob);
},
),
GFP_KERNEL,
@ -119,20 +127,16 @@ struct DeviceData {
}
fn init_control(base_dir: &Dir, dyn_dirs: Dir) -> impl PinInit<Scope<ModuleData>> + '_ {
base_dir.scope(
ModuleData::init(dyn_dirs),
c_str!("control"),
|data, dir| {
dir.write_only_callback_file(c_str!("create"), data, &create_file_write);
dir.write_only_callback_file(c_str!("remove"), data, &remove_file_write);
},
)
base_dir.scope(ModuleData::init(dyn_dirs), c"control", |data, dir| {
dir.write_only_callback_file(c"create", data, &create_file_write);
dir.write_only_callback_file(c"remove", data, &remove_file_write);
})
}
impl kernel::Module for RustScopedDebugFs {
fn init(_module: &'static kernel::ThisModule) -> Result<Self> {
let base_dir = Dir::new(c_str!("rust_scoped_debugfs"));
let dyn_dirs = base_dir.subdir(c_str!("dynamic"));
let base_dir = Dir::new(c"rust_scoped_debugfs");
let dyn_dirs = base_dir.subdir(c"dynamic");
Ok(Self {
_data: KBox::pin_init(init_control(&base_dir, dyn_dirs), GFP_KERNEL)?,
})

13
samples/rust/rust_dma.rs
View file

@ -57,7 +57,7 @@ impl pci::Driver for DmaSampleDriver {
fn probe(pdev: &pci::Device<Core>, _info: &Self::IdInfo) -> impl PinInit<Self, Error> {
pin_init::pin_init_scope(move || {
dev_info!(pdev.as_ref(), "Probe DMA test driver.\n");
dev_info!(pdev, "Probe DMA test driver.\n");
let mask = DmaMask::new::<64>();
@ -88,9 +88,7 @@ impl pci::Driver for DmaSampleDriver {
#[pinned_drop]
impl PinnedDrop for DmaSampleDriver {
fn drop(self: Pin<&mut Self>) {
let dev = self.pdev.as_ref();
dev_info!(dev, "Unload DMA test driver.\n");
dev_info!(self.pdev, "Unload DMA test driver.\n");
for (i, value) in TEST_VALUES.into_iter().enumerate() {
let val0 = kernel::dma_read!(self.ca[i].h);
@ -107,7 +105,12 @@ impl PinnedDrop for DmaSampleDriver {
}
for (i, entry) in self.sgt.iter().enumerate() {
dev_info!(dev, "Entry[{}]: DMA address: {:#x}", i, entry.dma_address());
dev_info!(
self.pdev,
"Entry[{}]: DMA address: {:#x}",
i,
entry.dma_address(),
);
}
}
}

14
samples/rust/rust_driver_auxiliary.rs
View file

@ -5,20 +5,22 @@
//! To make this driver probe, QEMU must be run with `-device pci-testdev`.
use kernel::{
auxiliary, c_str,
device::{Bound, Core},
auxiliary,
device::{
Bound,
Core, //
},
devres::Devres,
driver,
error::Error,
pci,
prelude::*,
InPlaceModule,
InPlaceModule, //
};
use core::any::TypeId;
const MODULE_NAME: &CStr = <LocalModule as kernel::ModuleMetadata>::NAME;
const AUXILIARY_NAME: &CStr = c_str!("auxiliary");
const AUXILIARY_NAME: &CStr = c"auxiliary";
struct AuxiliaryDriver;
@ -36,7 +38,7 @@ impl auxiliary::Driver for AuxiliaryDriver {
fn probe(adev: &auxiliary::Device<Core>, _info: &Self::IdInfo) -> impl PinInit<Self, Error> {
dev_info!(
adev.as_ref(),
adev,
"Probing auxiliary driver for auxiliary device with id={}\n",
adev.id()
);

10
samples/rust/rust_driver_faux.rs
View file

@ -2,7 +2,11 @@
//! Rust faux device sample.
use kernel::{c_str, faux, prelude::*, Module};
use kernel::{
faux,
prelude::*,
Module, //
};
module! {
type: SampleModule,
@ -20,9 +24,9 @@ impl Module for SampleModule {
fn init(_module: &'static ThisModule) -> Result<Self> {
pr_info!("Initialising Rust Faux Device Sample\n");
let reg = faux::Registration::new(c_str!("rust-faux-sample-device"), None)?;
let reg = faux::Registration::new(c"rust-faux-sample-device", None)?;
dev_info!(reg.as_ref(), "Hello from faux device!\n");
dev_info!(reg, "Hello from faux device!\n");
Ok(Self { _reg: reg })
}

43
samples/rust/rust_driver_pci.rs
View file

@ -4,7 +4,15 @@
//!
//! To make this driver probe, QEMU must be run with `-device pci-testdev`.
use kernel::{c_str, device::Core, devres::Devres, pci, prelude::*, sync::aref::ARef};
use kernel::{
device::Bound,
device::Core,
devres::Devres,
io::Io,
pci,
prelude::*,
sync::aref::ARef, //
};
struct Regs;
@ -58,6 +66,30 @@ impl SampleDriver {
Ok(bar.read32(Regs::COUNT))
}
fn config_space(pdev: &pci::Device<Bound>) {
let config = pdev.config_space();
// TODO: use the register!() macro for defining PCI configuration space registers once it
// has been move out of nova-core.
dev_info!(
pdev,
"pci-testdev config space read8 rev ID: {:x}\n",
config.read8(0x8)
);
dev_info!(
pdev,
"pci-testdev config space read16 vendor ID: {:x}\n",
config.read16(0)
);
dev_info!(
pdev,
"pci-testdev config space read32 BAR 0: {:x}\n",
config.read32(0x10)
);
}
}
impl pci::Driver for SampleDriver {
@ -69,7 +101,7 @@ impl pci::Driver for SampleDriver {
pin_init::pin_init_scope(move || {
let vendor = pdev.vendor_id();
dev_dbg!(
pdev.as_ref(),
pdev,
"Probe Rust PCI driver sample (PCI ID: {}, 0x{:x}).\n",
vendor,
pdev.device_id()
@ -79,16 +111,17 @@ impl pci::Driver for SampleDriver {
pdev.set_master();
Ok(try_pin_init!(Self {
bar <- pdev.iomap_region_sized::<{ Regs::END }>(0, c_str!("rust_driver_pci")),
bar <- pdev.iomap_region_sized::<{ Regs::END }>(0, c"rust_driver_pci"),
index: *info,
_: {
let bar = bar.access(pdev.as_ref())?;
dev_info!(
pdev.as_ref(),
pdev,
"pci-testdev data-match count: {}\n",
Self::testdev(info, bar)?
);
Self::config_space(pdev);
},
pdev: pdev.into(),
}))
@ -106,7 +139,7 @@ impl pci::Driver for SampleDriver {
#[pinned_drop]
impl PinnedDrop for SampleDriver {
fn drop(self: Pin<&mut Self>) {
dev_dbg!(self.pdev.as_ref(), "Remove Rust PCI driver sample.\n");
dev_dbg!(self.pdev, "Remove Rust PCI driver sample.\n");
}
}

42
samples/rust/rust_driver_platform.rs
View file

@ -63,16 +63,20 @@
//!
use kernel::{
acpi, c_str,
acpi,
device::{
self,
property::{FwNodeReferenceArgs, NArgs},
property::{
FwNodeReferenceArgs,
NArgs, //
},
Core,
},
of, platform,
of,
platform,
prelude::*,
str::CString,
sync::aref::ARef,
sync::aref::ARef, //
};
struct SampleDriver {
@ -85,14 +89,14 @@ kernel::of_device_table!(
OF_TABLE,
MODULE_OF_TABLE,
<SampleDriver as platform::Driver>::IdInfo,
[(of::DeviceId::new(c_str!("test,rust-device")), Info(42))]
[(of::DeviceId::new(c"test,rust-device"), Info(42))]
);
kernel::acpi_device_table!(
ACPI_TABLE,
MODULE_ACPI_TABLE,
<SampleDriver as platform::Driver>::IdInfo,
[(acpi::DeviceId::new(c_str!("LNUXBEEF")), Info(0))]
[(acpi::DeviceId::new(c"LNUXBEEF"), Info(0))]
);
impl platform::Driver for SampleDriver {
@ -124,49 +128,47 @@ impl SampleDriver {
fn properties_parse(dev: &device::Device) -> Result {
let fwnode = dev.fwnode().ok_or(ENOENT)?;
if let Ok(idx) =
fwnode.property_match_string(c_str!("compatible"), c_str!("test,rust-device"))
{
if let Ok(idx) = fwnode.property_match_string(c"compatible", c"test,rust-device") {
dev_info!(dev, "matched compatible string idx = {}\n", idx);
}
let name = c_str!("compatible");
let name = c"compatible";
let prop = fwnode.property_read::<CString>(name).required_by(dev)?;
dev_info!(dev, "'{name}'='{prop:?}'\n");
let name = c_str!("test,bool-prop");
let prop = fwnode.property_read_bool(c_str!("test,bool-prop"));
let name = c"test,bool-prop";
let prop = fwnode.property_read_bool(c"test,bool-prop");
dev_info!(dev, "'{name}'='{prop}'\n");
if fwnode.property_present(c_str!("test,u32-prop")) {
if fwnode.property_present(c"test,u32-prop") {
dev_info!(dev, "'test,u32-prop' is present\n");
}
let name = c_str!("test,u32-optional-prop");
let name = c"test,u32-optional-prop";
let prop = fwnode.property_read::<u32>(name).or(0x12);
dev_info!(dev, "'{name}'='{prop:#x}' (default = 0x12)\n");
// A missing required property will print an error. Discard the error to
// prevent properties_parse from failing in that case.
let name = c_str!("test,u32-required-prop");
let name = c"test,u32-required-prop";
let _ = fwnode.property_read::<u32>(name).required_by(dev);
let name = c_str!("test,u32-prop");
let name = c"test,u32-prop";
let prop: u32 = fwnode.property_read(name).required_by(dev)?;
dev_info!(dev, "'{name}'='{prop:#x}'\n");
let name = c_str!("test,i16-array");
let name = c"test,i16-array";
let prop: [i16; 4] = fwnode.property_read(name).required_by(dev)?;
dev_info!(dev, "'{name}'='{prop:?}'\n");
let len = fwnode.property_count_elem::<u16>(name)?;
dev_info!(dev, "'{name}' length is {len}\n");
let name = c_str!("test,i16-array");
let name = c"test,i16-array";
let prop: KVec<i16> = fwnode.property_read_array_vec(name, 4)?.required_by(dev)?;
dev_info!(dev, "'{name}'='{prop:?}' (KVec)\n");
for child in fwnode.children() {
let name = c_str!("test,ref-arg");
let name = c"test,ref-arg";
let nargs = NArgs::N(2);
let prop: FwNodeReferenceArgs = child.property_get_reference_args(name, nargs, 0)?;
dev_info!(dev, "'{name}'='{prop:?}'\n");
@ -178,7 +180,7 @@ impl SampleDriver {
impl Drop for SampleDriver {
fn drop(&mut self) {
dev_dbg!(self.pdev.as_ref(), "Remove Rust Platform driver sample.\n");
dev_dbg!(self.pdev, "Remove Rust Platform driver sample.\n");
}
}

79
samples/rust/rust_soc.rs Normal file
View file

@ -0,0 +1,79 @@
// SPDX-License-Identifier: GPL-2.0
//! Rust SoC Platform driver sample.
use kernel::{
acpi,
device::Core,
of,
platform,
prelude::*,
soc,
str::CString,
sync::aref::ARef, //
};
use pin_init::pin_init_scope;
#[pin_data]
struct SampleSocDriver {
pdev: ARef<platform::Device>,
#[pin]
_dev_reg: soc::Registration,
}
kernel::of_device_table!(
OF_TABLE,
MODULE_OF_TABLE,
<SampleSocDriver as platform::Driver>::IdInfo,
[(of::DeviceId::new(c"test,rust-device"), ())]
);
kernel::acpi_device_table!(
ACPI_TABLE,
MODULE_ACPI_TABLE,
<SampleSocDriver as platform::Driver>::IdInfo,
[(acpi::DeviceId::new(c"LNUXBEEF"), ())]
);
impl platform::Driver for SampleSocDriver {
type IdInfo = ();
const OF_ID_TABLE: Option<of::IdTable<Self::IdInfo>> = Some(&OF_TABLE);
const ACPI_ID_TABLE: Option<acpi::IdTable<Self::IdInfo>> = Some(&ACPI_TABLE);
fn probe(
pdev: &platform::Device<Core>,
_info: Option<&Self::IdInfo>,
) -> impl PinInit<Self, Error> {
dev_dbg!(pdev, "Probe Rust SoC driver sample.\n");
let pdev = pdev.into();
pin_init_scope(move || {
let machine = CString::try_from(c"My cool ACME15 dev board")?;
let family = CString::try_from(c"ACME")?;
let revision = CString::try_from(c"1.2")?;
let serial_number = CString::try_from(c"12345")?;
let soc_id = CString::try_from(c"ACME15")?;
let attr = soc::Attributes {
machine: Some(machine),
family: Some(family),
revision: Some(revision),
serial_number: Some(serial_number),
soc_id: Some(soc_id),
};
Ok(try_pin_init!(SampleSocDriver {
pdev: pdev,
_dev_reg <- soc::Registration::new(attr),
}? Error))
})
}
}
kernel::module_platform_driver! {
type: SampleSocDriver,
name: "rust_soc",
authors: ["Matthew Maurer"],
description: "Rust SoC Driver",
license: "GPL",
}