archives/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-03-13 23:46:14 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

drm/amdgpu: Fix xcc_id input for soc_v1_0_grbm_select

Browse source 
Ensure the GRBM_GFX_CNTL is programmed correctly

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang 2025-08-19 16:55:32 +08:00 • committed by Alex Deucher
parent 09a75a234b
commit bc35ae1a09
1 changed files with 4 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

8
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
View file

@ -1448,7 +1448,7 @@ static void gfx_v12_1_xcc_constants_init(struct amdgpu_device *adev,
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, tmp);
}
}
soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0));
soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
mutex_unlock(&adev->srbm_mutex);
@ -1776,7 +1776,7 @@ static void gfx_v12_1_xcc_config_gfx_rs64(struct amdgpu_device *adev,
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START_HI,
mec_hdr->ucode_start_addr_hi >> 2);
}
soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0));
soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
/* reset mec pipe */
tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL);
@ -1821,7 +1821,7 @@ static void gfx_v12_1_xcc_set_mec_ucode_start_addr(struct amdgpu_device *adev,
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START_HI,
cp_hdr->ucode_start_addr_hi >> 2);
}
soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0));
soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
mutex_unlock(&adev->srbm_mutex);
}
@ -2017,7 +2017,7 @@ static int gfx_v12_1_xcc_cp_compute_load_microcode_rs64(struct amdgpu_device *ad
upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
}
mutex_unlock(&adev->srbm_mutex);
soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0));
soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
/* Trigger an invalidation of the L1 instruction caches */
tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL);