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clk: thead: th1520-ap: Support CPU frequency scaling
On TH1520 SoC, c910_clk feeds the CPU cluster. It could be glitchlessly reparented to one of the two PLLs: either to cpu_pll0 indirectly through c910_i0_clk, or to cpu_pll1 directly. To achieve glitchless rate change, customized clock operations are implemented for c910_clk: on rate change, the PLL not currently in use is configured to the requested rate first, then c910_clk reparents to it. Additionally, c910_bus_clk, which in turn takes c910_clk as parent, has a frequency limit of 750MHz. A clock notifier is registered on c910_clk to adjust c910_bus_clk on c910_clk rate change. Reviewed-by: Drew Fustini <fustini@kernel.org> Signed-off-by: Yao Zi <ziyao@disroot.org> Signed-off-by: Drew Fustini <fustini@kernel.org>
This commit is contained in:
Yao Zi
Drew Fustini
parent
5dbee35037
commit
baf4fc7c03
1 changed files with 146 additions and 2 deletions
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@ -7,9 +7,11 @@
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#include <dt-bindings/clock/thead,th1520-clk-ap.h>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/minmax.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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@ -34,6 +36,9 @@
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#define TH1520_PLL_LOCK_TIMEOUT_US 44
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#define TH1520_PLL_STABLE_DELAY_US 30
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/* c910_bus_clk must be kept below 750MHz for stability */
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#define TH1520_C910_BUS_MAX_RATE (750 * 1000 * 1000)
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struct ccu_internal {
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u8 shift;
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u8 width;
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@ -472,6 +477,72 @@ static const struct clk_ops clk_pll_ops = {
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.set_rate = ccu_pll_set_rate,
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};
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/*
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* c910_clk could be reparented glitchlessly for DVFS. There are two parents,
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* - c910_i0_clk, derived from cpu_pll0_clk or osc_24m.
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* - cpu_pll1_clk, which provides the exact same set of rates as cpu_pll0_clk.
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*
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* During rate setting, always forward the request to the unused parent, and
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* then switch c910_clk to it to avoid glitch.
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*/
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static u8 c910_clk_get_parent(struct clk_hw *hw)
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{
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return clk_mux_ops.get_parent(hw);
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}
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static int c910_clk_set_parent(struct clk_hw *hw, u8 index)
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{
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return clk_mux_ops.set_parent(hw, index);
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}
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static unsigned long c910_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return parent_rate;
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}
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static int c910_clk_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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u8 alt_parent_index = !c910_clk_get_parent(hw);
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struct clk_hw *alt_parent;
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alt_parent = clk_hw_get_parent_by_index(hw, alt_parent_index);
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req->rate = clk_hw_round_rate(alt_parent, req->rate);
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req->best_parent_hw = alt_parent;
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req->best_parent_rate = req->rate;
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return 0;
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}
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static int c910_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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return -EOPNOTSUPP;
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}
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static int c910_clk_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate, u8 index)
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{
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struct clk_hw *parent = clk_hw_get_parent_by_index(hw, index);
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clk_set_rate(parent->clk, parent_rate);
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c910_clk_set_parent(hw, index);
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return 0;
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}
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static const struct clk_ops c910_clk_ops = {
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.get_parent = c910_clk_get_parent,
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.set_parent = c910_clk_set_parent,
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.recalc_rate = c910_clk_recalc_rate,
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.determine_rate = c910_clk_determine_rate,
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.set_rate = c910_clk_set_rate,
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.set_rate_and_parent = c910_clk_set_rate_and_parent,
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};
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static const struct clk_parent_data osc_24m_clk[] = {
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{ .index = 0 }
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};
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@ -672,7 +743,8 @@ static const struct clk_parent_data c910_i0_parents[] = {
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static struct ccu_mux c910_i0_clk = {
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.clkid = CLK_C910_I0,
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.reg = 0x100,
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.mux = TH_CCU_MUX("c910-i0", c910_i0_parents, 1, 1),
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.mux = TH_CCU_MUX_FLAGS("c910-i0", c910_i0_parents, 1, 1,
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CLK_SET_RATE_PARENT, CLK_MUX_ROUND_CLOSEST),
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};
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static const struct clk_parent_data c910_parents[] = {
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@ -683,7 +755,14 @@ static const struct clk_parent_data c910_parents[] = {
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static struct ccu_mux c910_clk = {
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.clkid = CLK_C910,
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.reg = 0x100,
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.mux = TH_CCU_MUX("c910", c910_parents, 0, 1),
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.mux = {
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.mask = BIT(0),
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.shift = 0,
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.hw.init = CLK_HW_INIT_PARENTS_DATA("c910",
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c910_parents,
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&c910_clk_ops,
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CLK_SET_RATE_PARENT),
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},
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};
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static struct ccu_div c910_bus_clk = {
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@ -1372,11 +1451,69 @@ static const struct th1520_plat_data th1520_vo_platdata = {
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.nr_gate_clks = ARRAY_SIZE(th1520_vo_gate_clks),
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};
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/*
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* Maintain clock rate of c910_bus_clk below TH1520_C910_BUS_MAX_RATE (750MHz)
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* when its parent, c910_clk, changes the rate.
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*
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* Additionally, TRM is unclear about c910_bus_clk behavior when the divisor is
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* set below 2, thus we should ensure the new divisor stays in (2, MAXDIVISOR).
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*/
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static unsigned long c910_bus_clk_divisor(struct ccu_div *cd,
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unsigned long parent_rate)
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{
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return clamp(DIV_ROUND_UP(parent_rate, TH1520_C910_BUS_MAX_RATE),
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2U, 1U << cd->div.width);
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}
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static int c910_clk_notifier_cb(struct notifier_block *nb,
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unsigned long action, void *data)
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{
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struct clk_notifier_data *cnd = data;
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unsigned long new_divisor, ref_rate;
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if (action != PRE_RATE_CHANGE && action != POST_RATE_CHANGE)
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return NOTIFY_DONE;
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new_divisor = c910_bus_clk_divisor(&c910_bus_clk, cnd->new_rate);
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if (cnd->new_rate > cnd->old_rate) {
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/*
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* Scaling up. Adjust c910_bus_clk divisor
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* - before c910_clk rate change to ensure the constraints
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* aren't broken after scaling to higher rates,
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* - after c910_clk rate change to keep c910_bus_clk as high as
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* possible
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*/
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ref_rate = action == PRE_RATE_CHANGE ?
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cnd->old_rate : cnd->new_rate;
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clk_set_rate(c910_bus_clk.common.hw.clk,
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ref_rate / new_divisor);
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} else if (cnd->new_rate < cnd->old_rate &&
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action == POST_RATE_CHANGE) {
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/*
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* Scaling down. Adjust c910_bus_clk divisor only after
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* c910_clk rate change to keep c910_bus_clk as high as
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* possible, Scaling down never breaks the constraints.
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*/
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clk_set_rate(c910_bus_clk.common.hw.clk,
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cnd->new_rate / new_divisor);
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} else {
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return NOTIFY_DONE;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block c910_clk_notifier = {
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.notifier_call = c910_clk_notifier_cb,
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};
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static int th1520_clk_probe(struct platform_device *pdev)
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{
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const struct th1520_plat_data *plat_data;
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struct device *dev = &pdev->dev;
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struct clk_hw_onecell_data *priv;
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struct clk *notifier_clk;
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struct regmap *map;
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void __iomem *base;
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@ -1463,6 +1600,13 @@ static int th1520_clk_probe(struct platform_device *pdev)
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ret = devm_clk_hw_register(dev, &emmc_sdio_ref_clk.hw);
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if (ret)
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return ret;
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notifier_clk = devm_clk_hw_get_clk(dev, &c910_clk.mux.hw,
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"dvfs");
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ret = devm_clk_notifier_register(dev, notifier_clk,
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&c910_clk_notifier);
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if (ret)
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return ret;
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}
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ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv);
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