dt-bindings: interrupt-controller: Convert marvell,orion-bridge-intc to DT schema

Convert the Marvell Orion bridge interrupt controller binding to schema
format.

marvell,orion-intc is already covered by mrvl,intc.yaml schema, so it
can be dropped.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20250505144743.1290672-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
This commit is contained in:
Rob Herring (Arm) 2025-05-05 09:47:42 -05:00
parent 5511d95c05
commit bac0fb596e
2 changed files with 52 additions and 48 deletions

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
---
$id: http://devicetree.org/schemas/interrupt-controller/marvell,orion-bridge-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Orion SoC Bridge Interrupt Controller
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
properties:
compatible:
const: marvell,orion-bridge-intc
reg:
minItems: 1
maxItems: 2
interrupt-controller: true
'#interrupt-cells':
const: 1
interrupts:
description: Bridge interrupt of the main interrupt controller
marvell,#interrupts:
description: Number of interrupts provided by bridge interrupt controller.
$ref: /schemas/types.yaml#/definitions/uint32
default: 32
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
- interrupts
additionalProperties: false
examples:
- |
interrupt-controller@20110 {
compatible = "marvell,orion-bridge-intc";
reg = <0x20110 0x8>;
interrupt-controller;
#interrupt-cells = <1>;
interrupts = <0>;
/* Dove bridge provides 5 interrupts */
marvell,#interrupts = <5>;
};

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Marvell Orion SoC interrupt controllers
* Main interrupt controller
Required properties:
- compatible: shall be "marvell,orion-intc"
- reg: base address(es) of interrupt registers starting with CAUSE register
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: number of cells to encode an interrupt source, shall be 1
The interrupt sources map to the corresponding bits in the interrupt
registers, i.e.
- 0 maps to bit 0 of first base address,
- 1 maps to bit 1 of first base address,
- 32 maps to bit 0 of second base address, and so on.
Example:
intc: interrupt-controller {
compatible = "marvell,orion-intc";
interrupt-controller;
#interrupt-cells = <1>;
/* Dove has 64 first level interrupts */
reg = <0x20200 0x10>, <0x20210 0x10>;
};
* Bridge interrupt controller
Required properties:
- compatible: shall be "marvell,orion-bridge-intc"
- reg: base address of bridge interrupt registers starting with CAUSE register
- interrupts: bridge interrupt of the main interrupt controller
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: number of cells to encode an interrupt source, shall be 1
Optional properties:
- marvell,#interrupts: number of interrupts provided by bridge interrupt
controller, defaults to 32 if not set
Example:
bridge_intc: interrupt-controller {
compatible = "marvell,orion-bridge-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x20110 0x8>;
interrupts = <0>;
/* Dove bridge provides 5 interrupts */
marvell,#interrupts = <5>;
};