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scsi: ufs: renesas: Add initialization code for R-Car S4-8 ES1.2
Add initialization code for R-Car S4-8 ES1.2 to improve transfer stability. Using the new code requires downloading firmware and reading calibration data from E-FUSE. If either fails, the driver falls back to the old initialization code. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Co-developed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/97d83709495c764b2456d4d25846f5f48197cad0.1741179611.git.geert+renesas@glider.be Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Yoshihiro Shimoda
Martin K. Petersen
parent
44ca16f497
commit
b3bb176245
1 changed files with 194 additions and 5 deletions
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@ -9,20 +9,31 @@
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/firmware.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/sys_soc.h>
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#include <ufs/ufshcd.h>
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#include "ufshcd-pltfrm.h"
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#define EFUSE_CALIB_SIZE 8
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struct ufs_renesas_priv {
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const struct firmware *fw;
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void (*pre_init)(struct ufs_hba *hba);
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bool initialized; /* The hardware needs initialization once */
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u8 calib[EFUSE_CALIB_SIZE];
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};
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#define UFS_RENESAS_FIRMWARE_NAME "r8a779f0_ufs.bin"
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MODULE_FIRMWARE(UFS_RENESAS_FIRMWARE_NAME);
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static void ufs_renesas_dbg_register_dump(struct ufs_hba *hba)
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{
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ufshcd_dump_regs(hba, 0xc0, 0x40, "regs: 0xc0 + ");
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@ -116,6 +127,22 @@ static void ufs_renesas_set_phy(struct ufs_hba *hba, u32 addr16, u32 data16)
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ufs_renesas_write_phy(hba, addr16, data16);
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}
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static void ufs_renesas_reset_indirect_write(struct ufs_hba *hba, int gpio,
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u32 addr, u32 data)
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{
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ufs_renesas_write(hba, 0xf0, gpio);
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ufs_renesas_write_800_80c_poll(hba, addr, data);
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}
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static void ufs_renesas_reset_indirect_update(struct ufs_hba *hba)
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{
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ufs_renesas_write_d0_d4(hba, 0x0000082c, 0x0f000000);
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ufs_renesas_write_d0_d4(hba, 0x00000828, 0x0f000000);
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ufs_renesas_write(hba, 0xd0, 0x0000082c);
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ufs_renesas_poll(hba, 0xd4, BIT(27) | BIT(26) | BIT(24), BIT(27) | BIT(26) | BIT(24));
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ufs_renesas_write(hba, 0xf0, 0);
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}
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static void ufs_renesas_indirect_write(struct ufs_hba *hba, u32 gpio, u32 addr,
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u32 data_800)
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{
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@ -135,15 +162,19 @@ static void ufs_renesas_indirect_poll(struct ufs_hba *hba, u32 gpio, u32 addr,
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ufs_renesas_write(hba, 0xf0, 0);
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}
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static void ufs_renesas_init_step1_to_3(struct ufs_hba *hba)
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static void ufs_renesas_init_step1_to_3(struct ufs_hba *hba, bool init108)
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{
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ufs_renesas_write(hba, 0xc0, 0x49425308);
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ufs_renesas_write_d0_d4(hba, 0x00000104, 0x00000002);
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if (init108)
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ufs_renesas_write_d0_d4(hba, 0x00000108, 0x00000002);
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udelay(1);
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ufs_renesas_write_d0_d4(hba, 0x00000828, 0x00000200);
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udelay(1);
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ufs_renesas_write_d0_d4(hba, 0x00000828, 0x00000000);
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ufs_renesas_write_d0_d4(hba, 0x00000104, 0x00000001);
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if (init108)
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ufs_renesas_write_d0_d4(hba, 0x00000108, 0x00000001);
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ufs_renesas_write_d0_d4(hba, 0x00000940, 0x00000001);
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udelay(1);
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ufs_renesas_write_d0_d4(hba, 0x00000940, 0x00000000);
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@ -207,12 +238,12 @@ static void ufs_renesas_init_compensation_and_slicers(struct ufs_hba *hba)
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ufs_renesas_write_phy_10ad_10af(hba, 0x0080, 0x001a);
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}
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static void ufs_renesas_pre_init(struct ufs_hba *hba)
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static void ufs_renesas_r8a779f0_es10_pre_init(struct ufs_hba *hba)
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{
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u32 timer_val;
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/* This setting is for SERIES B */
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ufs_renesas_init_step1_to_3(hba);
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ufs_renesas_init_step1_to_3(hba, false);
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ufs_renesas_init_step4_to_6(hba);
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@ -283,6 +314,105 @@ static void ufs_renesas_pre_init(struct ufs_hba *hba)
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ufs_renesas_init_enable_timer(hba, timer_val);
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}
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static void ufs_renesas_r8a779f0_init_step3_add(struct ufs_hba *hba, bool assert)
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{
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u32 val_2x = 0, val_3x = 0, val_4x = 0;
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if (assert) {
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val_2x = 0x0001;
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val_3x = 0x0003;
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val_4x = 0x0001;
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}
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ufs_renesas_reset_indirect_write(hba, 7, 0x20, val_2x);
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ufs_renesas_reset_indirect_write(hba, 7, 0x4a, val_4x);
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ufs_renesas_reset_indirect_write(hba, 7, 0x35, val_3x);
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ufs_renesas_reset_indirect_update(hba);
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ufs_renesas_reset_indirect_write(hba, 7, 0x21, val_2x);
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ufs_renesas_reset_indirect_write(hba, 7, 0x4b, val_4x);
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ufs_renesas_reset_indirect_write(hba, 7, 0x36, val_3x);
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ufs_renesas_reset_indirect_update(hba);
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}
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static void ufs_renesas_r8a779f0_pre_init(struct ufs_hba *hba)
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{
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struct ufs_renesas_priv *priv = ufshcd_get_variant(hba);
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u32 timer_val;
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u32 data;
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int i;
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/* This setting is for SERIES B */
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ufs_renesas_init_step1_to_3(hba, true);
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ufs_renesas_r8a779f0_init_step3_add(hba, true);
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ufs_renesas_reset_indirect_write(hba, 7, 0x5f, 0x0063);
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ufs_renesas_reset_indirect_update(hba);
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ufs_renesas_reset_indirect_write(hba, 7, 0x60, 0x0003);
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ufs_renesas_reset_indirect_update(hba);
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ufs_renesas_reset_indirect_write(hba, 7, 0x5b, 0x00a6);
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ufs_renesas_reset_indirect_update(hba);
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ufs_renesas_reset_indirect_write(hba, 7, 0x5c, 0x0003);
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ufs_renesas_reset_indirect_update(hba);
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ufs_renesas_r8a779f0_init_step3_add(hba, false);
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ufs_renesas_init_step4_to_6(hba);
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timer_val = ufs_renesas_init_disable_timer(hba);
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ufs_renesas_indirect_write(hba, 1, 0x01, 0x001f);
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ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0014);
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ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0014);
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ufs_renesas_indirect_write(hba, 7, 0x0d, 0x0007);
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ufs_renesas_indirect_write(hba, 7, 0x0e, 0x0007);
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ufs_renesas_indirect_poll(hba, 7, 0x3c, 0, BIT(7));
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ufs_renesas_indirect_poll(hba, 7, 0x4c, 0, BIT(4));
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ufs_renesas_indirect_write(hba, 1, 0x32, 0x0080);
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ufs_renesas_indirect_write(hba, 1, 0x1f, 0x0001);
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ufs_renesas_indirect_write(hba, 1, 0x2c, 0x0001);
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ufs_renesas_indirect_write(hba, 1, 0x32, 0x0087);
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ufs_renesas_indirect_write(hba, 1, 0x4d, priv->calib[2]);
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ufs_renesas_indirect_write(hba, 1, 0x4e, priv->calib[3]);
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ufs_renesas_indirect_write(hba, 1, 0x0d, 0x0006);
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ufs_renesas_indirect_write(hba, 1, 0x0e, 0x0007);
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ufs_renesas_write_phy(hba, 0x0028, priv->calib[3]);
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ufs_renesas_write_phy(hba, 0x4014, priv->calib[3]);
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ufs_renesas_set_phy(hba, 0x401c, BIT(2));
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ufs_renesas_write_phy(hba, 0x4000, priv->calib[6]);
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ufs_renesas_write_phy(hba, 0x4001, priv->calib[7]);
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ufs_renesas_indirect_write(hba, 1, 0x14, 0x0001);
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ufs_renesas_init_compensation_and_slicers(hba);
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ufs_renesas_indirect_write(hba, 7, 0x79, 0x0000);
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ufs_renesas_indirect_write(hba, 7, 0x24, 0x000c);
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ufs_renesas_indirect_write(hba, 7, 0x25, 0x000c);
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ufs_renesas_indirect_write(hba, 7, 0x62, 0x00c0);
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ufs_renesas_indirect_write(hba, 7, 0x63, 0x0001);
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for (i = 0; i < priv->fw->size / 2; i++) {
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data = (priv->fw->data[i * 2 + 1] << 8) | priv->fw->data[i * 2];
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ufs_renesas_write_phy(hba, 0xc000 + i, data);
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}
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ufs_renesas_indirect_write(hba, 7, 0x0d, 0x0002);
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ufs_renesas_indirect_write(hba, 7, 0x0e, 0x0007);
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ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0014);
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ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0017);
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ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0004);
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ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0017);
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ufs_renesas_indirect_poll(hba, 7, 0x55, 0, BIT(6));
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ufs_renesas_indirect_poll(hba, 7, 0x41, 0, BIT(7));
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ufs_renesas_init_enable_timer(hba, timer_val);
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}
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static int ufs_renesas_hce_enable_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status status)
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{
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@ -292,7 +422,7 @@ static int ufs_renesas_hce_enable_notify(struct ufs_hba *hba,
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return 0;
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if (status == PRE_CHANGE)
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ufs_renesas_pre_init(hba);
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priv->pre_init(hba);
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priv->initialized = true;
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@ -310,20 +440,78 @@ static int ufs_renesas_setup_clocks(struct ufs_hba *hba, bool on,
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return 0;
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}
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static const struct soc_device_attribute ufs_fallback[] = {
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{ .soc_id = "r8a779f0", .revision = "ES1.[01]" },
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{ /* Sentinel */ }
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};
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static int ufs_renesas_init(struct ufs_hba *hba)
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{
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const struct soc_device_attribute *attr;
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struct nvmem_cell *cell = NULL;
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struct device *dev = hba->dev;
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struct ufs_renesas_priv *priv;
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u8 *data = NULL;
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size_t len;
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int ret;
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priv = devm_kzalloc(hba->dev, sizeof(*priv), GFP_KERNEL);
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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ufshcd_set_variant(hba, priv);
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hba->quirks |= UFSHCD_QUIRK_HIBERN_FASTAUTO;
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attr = soc_device_match(ufs_fallback);
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if (attr)
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goto fallback;
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ret = request_firmware(&priv->fw, UFS_RENESAS_FIRMWARE_NAME, dev);
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if (ret) {
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dev_warn(dev, "Failed to load firmware\n");
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goto fallback;
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}
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cell = nvmem_cell_get(dev, "calibration");
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if (IS_ERR(cell)) {
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dev_warn(dev, "No calibration data specified\n");
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goto fallback;
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}
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data = nvmem_cell_read(cell, &len);
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if (IS_ERR(data)) {
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dev_warn(dev, "Failed to read calibration data: %pe\n", data);
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goto fallback;
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}
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if (len != EFUSE_CALIB_SIZE) {
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dev_warn(dev, "Invalid calibration data size %zu\n", len);
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goto fallback;
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}
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memcpy(priv->calib, data, EFUSE_CALIB_SIZE);
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priv->pre_init = ufs_renesas_r8a779f0_pre_init;
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goto out;
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fallback:
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dev_info(dev, "Using ES1.0 init code\n");
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priv->pre_init = ufs_renesas_r8a779f0_es10_pre_init;
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out:
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kfree(data);
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if (!IS_ERR_OR_NULL(cell))
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nvmem_cell_put(cell);
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return 0;
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}
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static void ufs_renesas_exit(struct ufs_hba *hba)
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{
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struct ufs_renesas_priv *priv = ufshcd_get_variant(hba);
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release_firmware(priv->fw);
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}
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static int ufs_renesas_set_dma_mask(struct ufs_hba *hba)
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{
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return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
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@ -332,6 +520,7 @@ static int ufs_renesas_set_dma_mask(struct ufs_hba *hba)
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static const struct ufs_hba_variant_ops ufs_renesas_vops = {
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.name = "renesas",
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.init = ufs_renesas_init,
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.exit = ufs_renesas_exit,
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.set_dma_mask = ufs_renesas_set_dma_mask,
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.setup_clocks = ufs_renesas_setup_clocks,
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.hce_enable_notify = ufs_renesas_hce_enable_notify,
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