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Miscellaneous fixes:
- Fix BCM2712 irqchip driver Kconfig dependencies
required on the Raspberry PI5
- Fix spurious interrupts on RZ/G3E SMARC EVK systems
- Fix crash regression on Sun/NIU hardware
- Apply MSI driver quirk for Sun Neptune chips
Signed-off-by: Ingo Molnar <mingo@kernel.org>
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Merge tag 'irq-urgent-2025-04-18' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull misc irq fixes from Ingo Molnar:
- Fix BCM2712 irqchip driver Kconfig dependencies required on the
Raspberry PI5
- Fix spurious interrupts on RZ/G3E SMARC EVK systems
- Fix crash regression on Sun/NIU hardware
- Apply MSI driver quirk for Sun Neptune chips
* tag 'irq-urgent-2025-04-18' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqchip/irq-bcm2712-mip: Enable driver when ARCH_BCM2835 is enabled
irqchip/renesas-rzv2h: Prevent TINT spurious interrupt
net/niu: Niu requires MSIX ENTRY_DATA fields touch before entry reads
PCI/MSI: Add an option to write MSIX ENTRY_DATA before any reads
This commit is contained in:
commit
b0c3bc35a5
5 changed files with 17 additions and 2 deletions
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@ -114,8 +114,8 @@ config I8259
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config BCM2712_MIP
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tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support"
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depends on ARCH_BRCMSTB || COMPILE_TEST
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default m if ARCH_BRCMSTB
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depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST
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default m if ARCH_BRCMSTB || ARCH_BCM2835
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depends on ARM_GIC
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN_HIERARCHY
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@ -170,6 +170,14 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable)
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else
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tssr &= ~ICU_TSSR_TIEN(tssel_n, priv->info->field_width);
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writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k));
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/*
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* A glitch in the edge detection circuit can cause a spurious
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* interrupt. Clear the status flag after setting the ICU_TSSRk
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* registers, which is recommended by the hardware manual as a
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* countermeasure.
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*/
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writel_relaxed(BIT(tint_nr), priv->base + priv->info->t_offs + ICU_TSCLR);
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}
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static void rzv2h_icu_irq_disable(struct irq_data *d)
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@ -9064,6 +9064,8 @@ static void niu_try_msix(struct niu *np, u8 *ldg_num_map)
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msi_vec[i].entry = i;
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}
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pdev->dev_flags |= PCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST;
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num_irqs = pci_enable_msix_range(pdev, msi_vec, 1, num_irqs);
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if (num_irqs < 0) {
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np->flags &= ~NIU_FLAGS_MSIX;
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@ -615,6 +615,9 @@ void msix_prepare_msi_desc(struct pci_dev *dev, struct msi_desc *desc)
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void __iomem *addr = pci_msix_desc_addr(desc);
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desc->pci.msi_attrib.can_mask = 1;
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/* Workaround for SUN NIU insanity, which requires write before read */
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if (dev->dev_flags & PCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST)
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writel(0, addr + PCI_MSIX_ENTRY_DATA);
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desc->pci.msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
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}
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}
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@ -245,6 +245,8 @@ enum pci_dev_flags {
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PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
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/* Device does honor MSI masking despite saying otherwise */
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PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
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/* Device requires write to PCI_MSIX_ENTRY_DATA before any MSIX reads */
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PCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = (__force pci_dev_flags_t) (1 << 13),
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};
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enum pci_irq_reroute_variant {
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