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Merge branch 'pci/controller/aspeed'
- Add ASPEED Root Complex DT binding and driver (Jacky Chou) * pci/controller/aspeed: MAINTAINERS: Add ASPEED PCIe RC driver PCI: aspeed: Add ASPEED PCIe RC driver PCI: Add FMT, TYPE and CPL status definition for TLP header dt-bindings: PCI: Add ASPEED PCIe RC support
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Bjorn Helgaas
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182
Documentation/devicetree/bindings/pci/aspeed,ast2600-pcie.yaml
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182
Documentation/devicetree/bindings/pci/aspeed,ast2600-pcie.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/aspeed,ast2600-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ASPEED PCIe Root Complex Controller
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maintainers:
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- Jacky Chou <jacky_chou@aspeedtech.com>
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description:
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The ASPEED PCIe Root Complex controller provides PCI Express Root Complex
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functionality for ASPEED SoCs, such as the AST2600 and AST2700.
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This controller enables connectivity to PCIe endpoint devices, supporting
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memory and I/O windows, MSI and INTx interrupts, and integration with
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the SoC's clock, reset, and pinctrl subsystems. On AST2600, the PCIe Root
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Port device number is always 8.
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properties:
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compatible:
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enum:
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- aspeed,ast2600-pcie
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- aspeed,ast2700-pcie
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reg:
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maxItems: 1
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ranges:
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minItems: 2
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maxItems: 2
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interrupts:
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maxItems: 1
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description: INTx and MSI interrupt
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resets:
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items:
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- description: PCIe controller reset
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reset-names:
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items:
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- const: h2x
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aspeed,ahbc:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the ASPEED AHB Controller (AHBC) syscon node.
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This reference is used by the PCIe controller to access
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system-level configuration registers related to the AHB bus.
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To enable AHB access for the PCIe controller.
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aspeed,pciecfg:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the ASPEED PCIe configuration syscon node.
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This reference allows the PCIe controller to access
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SoC-specific PCIe configuration registers. There are the others
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functions such PCIe RC and PCIe EP will use this common register
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to configure the SoC interfaces.
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interrupt-controller: true
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patternProperties:
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"^pcie@[0-9a-f]+,0$":
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type: object
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$ref: /schemas/pci/pci-pci-bridge.yaml#
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properties:
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reg:
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maxItems: 1
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resets:
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items:
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- description: PERST# signal
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reset-names:
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items:
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- const: perst
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clocks:
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maxItems: 1
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phys:
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maxItems: 1
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required:
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- resets
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- reset-names
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- clocks
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- phys
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- ranges
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unevaluatedProperties: false
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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- $ref: /schemas/interrupt-controller/msi-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: aspeed,ast2600-pcie
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then:
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required:
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- aspeed,ahbc
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else:
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properties:
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aspeed,ahbc: false
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- if:
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properties:
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compatible:
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contains:
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const: aspeed,ast2700-pcie
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then:
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required:
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- aspeed,pciecfg
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else:
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properties:
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aspeed,pciecfg: false
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required:
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- reg
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- interrupts
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- bus-range
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- ranges
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- resets
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- reset-names
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- msi-controller
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- interrupt-controller
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- interrupt-map-mask
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- interrupt-map
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/ast2600-clock.h>
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pcie0: pcie@1e770000 {
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compatible = "aspeed,ast2600-pcie";
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device_type = "pci";
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reg = <0x1e770000 0x100>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000
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0x02000000 0x0 0x60000000 0x60000000 0x0 0x20000000>;
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resets = <&syscon ASPEED_RESET_H2X>;
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reset-names = "h2x";
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#interrupt-cells = <1>;
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msi-controller;
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aspeed,ahbc = <&ahbc>;
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interrupt-controller;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie0 0>,
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<0 0 0 2 &pcie0 1>,
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<0 0 0 3 &pcie0 2>,
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<0 0 0 4 &pcie0 3>;
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pcie@8,0 {
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compatible = "pciclass,0604";
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reg = <0x00004000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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resets = <&syscon ASPEED_RESET_PCIE_RC_O>;
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reset-names = "perst";
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clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcierc1_default>;
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phys = <&pcie_phy1>;
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ranges;
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};
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};
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@ -3902,6 +3902,14 @@ S: Maintained
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F: Documentation/devicetree/bindings/media/aspeed,video-engine.yaml
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F: drivers/media/platform/aspeed/
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ASPEED PCIE CONTROLLER DRIVER
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M: Jacky Chou <jacky_chou@aspeedtech.com>
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L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
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L: linux-pci@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/aspeed,ast2600-pcie.yaml
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F: drivers/pci/controller/pcie-aspeed.c
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ASUS EC HARDWARE MONITOR DRIVER
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M: Eugene Shalygin <eugene.shalygin@gmail.com>
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L: linux-hwmon@vger.kernel.org
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@ -58,6 +58,22 @@ config PCI_VERSATILE
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bool "ARM Versatile PB PCI controller"
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depends on ARCH_VERSATILE || COMPILE_TEST
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config PCIE_ASPEED
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bool "ASPEED PCIe controller"
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depends on ARCH_ASPEED || COMPILE_TEST
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depends on OF
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depends on PCI_MSI
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select IRQ_MSI_LIB
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help
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Enable this option to support the PCIe controller found on ASPEED
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SoCs.
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This driver provides initialization and management for PCIe
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Root Complex functionality, including INTx and MSI support.
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Select Y if your platform uses an ASPEED SoC and requires PCIe
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connectivity.
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config PCIE_BRCMSTB
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tristate "Broadcom Brcmstb PCIe controller"
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depends on ARCH_BRCMSTB || ARCH_BCM2835 || ARCH_BCMBCA || \
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@ -40,6 +40,7 @@ obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
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obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o
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obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o
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obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o
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obj-$(CONFIG_PCIE_ASPEED) += pcie-aspeed.o
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# pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
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obj-y += dwc/
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1111
drivers/pci/controller/pcie-aspeed.c
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1111
drivers/pci/controller/pcie-aspeed.c
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File diff suppressed because it is too large
Load diff
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@ -64,6 +64,18 @@ struct pcie_tlp_log;
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#define PCIE_LINK_WAIT_MAX_RETRIES 10
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#define PCIE_LINK_WAIT_SLEEP_MS 90
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/* Format of TLP; PCIe r7.0, sec 2.2.1 */
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#define PCIE_TLP_FMT_3DW_NO_DATA 0x00 /* 3DW header, no data */
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#define PCIE_TLP_FMT_4DW_NO_DATA 0x01 /* 4DW header, no data */
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#define PCIE_TLP_FMT_3DW_DATA 0x02 /* 3DW header, with data */
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#define PCIE_TLP_FMT_4DW_DATA 0x03 /* 4DW header, with data */
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/* Type of TLP; PCIe r7.0, sec 2.2.1 */
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#define PCIE_TLP_TYPE_CFG0_RD 0x04 /* Config Type 0 Read Request */
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#define PCIE_TLP_TYPE_CFG0_WR 0x04 /* Config Type 0 Write Request */
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#define PCIE_TLP_TYPE_CFG1_RD 0x05 /* Config Type 1 Read Request */
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#define PCIE_TLP_TYPE_CFG1_WR 0x05 /* Config Type 1 Write Request */
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/* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */
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#define PCIE_MSG_TYPE_R_RC 0
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#define PCIE_MSG_TYPE_R_ADDR 1
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@ -85,6 +97,9 @@ struct pcie_tlp_log;
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#define PCIE_MSG_CODE_DEASSERT_INTC 0x26
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#define PCIE_MSG_CODE_DEASSERT_INTD 0x27
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/* Cpl. status of Complete; PCIe r7.0, sec 2.2.9.1 */
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#define PCIE_CPL_STS_SUCCESS 0x00 /* Successful Completion */
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#define PCI_BUS_BRIDGE_IO_WINDOW 0
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#define PCI_BUS_BRIDGE_MEM_WINDOW 1
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#define PCI_BUS_BRIDGE_PREF_MEM_WINDOW 2
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