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dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema

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Convert the RISC-V Hart-Level Interrupt Controller (HLIC) to newer
DT schema, Created DT schema based on the .txt file which had
`compatible`, `#interrupt-cells` and `interrupt-controller` as
required properties.
Changes made with respect to original file:
- Changed the example to just use interrupt-controller instead of
using the whole cpu block
- Changed the example compatible string.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Kanak Shilledar <kanakshilledar@gmail.com>
Link: https://lore.kernel.org/r/20240615021507.122035-2-kanakshilledar@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Kanak Shilledar 2024-06-15 07:45:03 +05:30 • committed by Palmer Dabbelt
parent 1613e604df
commit 9ff141042a
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2 changed files with 73 additions and 52 deletions
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52
Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
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RISC-V Hart-Level Interrupt Controller (HLIC)
---------------------------------------------
RISC-V cores include Control Status Registers (CSRs) which are local to each
CPU core (HART in RISC-V terminology) and can be read or written by software.
Some of these CSRs are used to control local interrupts connected to the core.
Every interrupt is ultimately routed through a hart's HLIC before it
interrupts that hart.
The RISC-V supervisor ISA manual specifies three interrupt sources that are
attached to every HLIC: software interrupts, the timer interrupt, and external
interrupts. Software interrupts are used to send IPIs between cores. The
timer interrupt comes from an architecturally mandated real-time timer that is
controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
interrupts connect all other device interrupts to the HLIC, which are routed
via the platform-level interrupt controller (PLIC).
All RISC-V systems that conform to the supervisor ISA specification are
required to have a HLIC with these three interrupt sources present. Since the
interrupt map is defined by the ISA it's not listed in the HLIC's device tree
entry, though external interrupt controllers (like the PLIC, for example) will
need to define how their interrupts map to the relevant HLICs. This means
a PLIC interrupt property will typically list the HLICs for all present HARTs
in the system.
Required properties:
- compatible : "riscv,cpu-intc"
- #interrupt-cells : should be <1>. The interrupt sources are defined by the
RISC-V supervisor ISA manual, with only the following three interrupts being
defined for supervisor mode:
- Source 1 is the supervisor software interrupt, which can be sent by an SBI
call and is reserved for use by software.
- Source 5 is the supervisor timer interrupt, which can be configured by
SBI calls and implements a one-shot timer.
- Source 9 is the supervisor external interrupt, which chains to all other
device interrupts.
- interrupt-controller : Identifies the node as an interrupt controller
Furthermore, this interrupt-controller MUST be embedded inside the cpu
definition of the hart whose CSRs control these local interrupts.
An example device tree entry for a HLIC is show below.
cpu1: cpu@1 {
compatible = "riscv";
...
cpu1-intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc";
interrupt-controller;
};
};

73
Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: RISC-V Hart-Level Interrupt Controller (HLIC)
description:
RISC-V cores include Control Status Registers (CSRs) which are local to
each CPU core (HART in RISC-V terminology) and can be read or written by
software. Some of these CSRs are used to control local interrupts connected
to the core. Every interrupt is ultimately routed through a hart's HLIC
before it interrupts that hart.
The RISC-V supervisor ISA manual specifies three interrupt sources that are
attached to every HLIC namely software interrupts, the timer interrupt, and
external interrupts. Software interrupts are used to send IPIs between
cores. The timer interrupt comes from an architecturally mandated real-
time timer that is controlled via Supervisor Binary Interface (SBI) calls
and CSR reads. External interrupts connect all other device interrupts to
the HLIC, which are routed via the platform-level interrupt controller
(PLIC).
All RISC-V systems that conform to the supervisor ISA specification are
required to have a HLIC with these three interrupt sources present. Since
the interrupt map is defined by the ISA it's not listed in the HLIC's device
tree entry, though external interrupt controllers (like the PLIC, for
example) will need to define how their interrupts map to the relevant HLICs.
This means a PLIC interrupt property will typically list the HLICs for all
present HARTs in the system.
maintainers:
- Palmer Dabbelt <palmer@dabbelt.com>
- Paul Walmsley <paul.walmsley@sifive.com>
properties:
compatible:
oneOf:
- items:
- const: andestech,cpu-intc
- const: riscv,cpu-intc
- const: riscv,cpu-intc
interrupt-controller: true
'#interrupt-cells':
const: 1
description: |
The interrupt sources are defined by the RISC-V supervisor ISA manual,
with only the following three interrupts being defined for
supervisor mode:
- Source 1 is the supervisor software interrupt, which can be sent by
an SBI call and is reserved for use by software.
- Source 5 is the supervisor timer interrupt, which can be configured
by SBI calls and implements a one-shot timer.
- Source 9 is the supervisor external interrupt, which chains to all
other device interrupts.
required:
- compatible
- '#interrupt-cells'
- interrupt-controller
additionalProperties: false
examples:
- |
interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};